Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Avoiding multisource in VHDL

Reply
Thread Tools

Avoiding multisource in VHDL

 
 
fpgawizz
Guest
Posts: n/a
 
      04-09-2005
I have a design where i have data coming in from a serial port, i am
sampling it and then writing to an external SRAM. Everything is fine until
now. I have an FSM that does this process for me.

I also have another input which when asserted should make my circuit check
if the data i wrote to the SRAM is correct. like a simple read and compare
against expected value. I am also writing the values to an internal block
ram for use in comparison later. The issue here is I have a process
statement that has my FSM which goes from address 0 to N to write my seial
data to SRAM. If I have another process statement to execute the read and
compare, I wont be able to use the signals i have for address since they
are used in the serial receive process statement.

Also i dont want to put this logic inside the serial process statement coz
it would make it complicated.
How do i have a second process statement and yet avoid multisource errors
on my address out lines?

Signal "N"(8 bits) maps to "addr_in"(8 bits). addr_in is the inout of my
memory controller state machine. I increment N and write the data coming
in to the SRAM. I want to manipulate N again when the read and execute
operation is asserted. Any ideas how i can achieve this?
thanks

 
Reply With Quote
 
 
 
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      04-09-2005
fpgawizz wrote:
> I have a design where i have data coming in from a serial port, i am
> sampling it and then writing to an external SRAM. Everything is fine until
> now. I have an FSM that does this process for me.
>
> I also have another input which when asserted should make my circuit check
> if the data i wrote to the SRAM is correct. like a simple read and compare
> against expected value. I am also writing the values to an internal block
> ram for use in comparison later. The issue here is I have a process
> statement that has my FSM which goes from address 0 to N to write my seial
> data to SRAM. If I have another process statement to execute the read and
> compare, I wont be able to use the signals i have for address since they
> are used in the serial receive process statement.
>
> Also i dont want to put this logic inside the serial process statement coz
> it would make it complicated.


Well .. I guess at the end it is easier to build a FSM, that is capable
of doing both jobs (the normal RAM-access and the check-access). This
would aslso save chip area.

Nevertheless it is possible to access the RAM from more than one
process. You need a signal, that decides, which FSM (normal RAM-access
or check-access) is running at the moment and which one has to be "silent".
The same signal controls a simple mux / demux, where the
RAM-access-signals (cs, we, addr, data) are selected from one of the FSMs.

The decision-signal may be provided by another state machine or all
state machines, that have RAM-access should "negotiate": The
normal-RAM-access FSM may provide a signal, that tells the
check-RAM-access FSM, that it now can operate and the check-RAM FSM
provides a signal, which tells the other FSM, that it has finished.

Short: You need one or more decision / negotiation signals and muxes /
demuxes.




Ralf
 
Reply With Quote
 
 
 
 
fpgawizz
Guest
Posts: n/a
 
      04-09-2005
Ralf:
Can you give me an idea of how to turn off an FSM/turn on an FSM using
this "Decide" signal?



 
Reply With Quote
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      04-09-2005
fpgawizz wrote:

> Can you give me an idea of how to turn off an FSM/turn on an FSM using
> this "Decide" signal?


Define a state, where the FSM is "idle" and checking this
"decide-signal". Jump to the next state only, if the "decide-signal"
grants access - otherwise stay in the idle-state and do nothing.

An idle-state is nessecary, as the FSM must not drive the cs, we, addr
and data signals to the RAM.

If a RAM access is performed, the FSM cannot be interrupted. (What would
happen, if otherwise?) After the access is complete, the FSM may jump to
the idle-state and decide, if it can perform another access or grants
bus-access to another FSM.



And here you may see, that it would be easy to implement the
RAM-check-functionality in the same FSM as the normal
RAM-acces-functionality. The FSM only would have to decide which branch
it should take. No (explicit) mux for the RAM-bus is nessecary.


Ralf
 
Reply With Quote
 
info_
Guest
Posts: n/a
 
      04-11-2005
fpgawizz wrote:
> I have a design where i have data coming in from a serial port, i am
> sampling it and then writing to an external SRAM. Everything is fine until
> now. I have an FSM that does this process for me.
>
> I also have another input which when asserted should make my circuit check
> if the data i wrote to the SRAM is correct. like a simple read and compare
> against expected value. I am also writing the values to an internal block
> ram for use in comparison later. The issue here is I have a process
> statement that has my FSM which goes from address 0 to N to write my seial
> data to SRAM. If I have another process statement to execute the read and
> compare, I wont be able to use the signals i have for address since they
> are used in the serial receive process statement.
>
> Also i dont want to put this logic inside the serial process statement coz
> it would make it complicated.
> How do i have a second process statement and yet avoid multisource errors
> on my address out lines?
>
> Signal "N"(8 bits) maps to "addr_in"(8 bits). addr_in is the inout of my
> memory controller state machine. I increment N and write the data coming
> in to the SRAM. I want to manipulate N again when the read and execute
> operation is asserted. Any ideas how i can achieve this?
> thanks
>

What you're asking for is probably an inefficient solution IMO...

Anyway : you can drive a signal from several sources by simply
"OR"ing the two sources... and making sure they do not drive
at the same time, in which case the mess is guaranteed...
Same for data by "AND"ing the Douts of each side with the
mutually exclusive SELects.

Making "independent" stuffs share a common is ressource isn't
for much fun.

I suggest you review the way you plan your system, and write a
single "ressource controller" handling both tasks. It's easier to
design, easier to verify and prove right, and probably much
more efficient anyway.

Bert Cuzeau
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
VHDL'87: avoiding FATAL ERROR when "Failed to open VHDL file" occurs sigwalt@gmx.net VHDL 2 09-04-2007 09:06 PM
VHDL'87: avoiding that "file not found" leads to fatal error sigwalt Hardware 0 09-04-2007 10:30 AM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
Multisource Signal workaround RishiD VHDL 4 11-02-2006 12:00 PM
what's the difference between VHDL 93 CONCATENATION and VHDL 87 CONCATENATION? walala VHDL 3 09-18-2003 04:17 AM



Advertisments