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Validation Engineer

We are looking for a Validation Engineer to verify VLSI Logic
Simulation Products. You will be part of a team that is developing and
delivering a Hardware Accelerator for Logic Simulation. You will be
responsible for developing and implementing test plans for features of
a Verilog/VHDL Simulation Accelerator. You will create Verilog/VHDL
Modeling and Verification IP.

Requirements:

BS/MS EE/CS with 1-2 years relevant experience

Experience with Verilog or VHDL Coding

Experience with one or more of VCS, NC-Verilog, Modelsim Simulators

Experience with Synthesis Tools

Experience with Verilog/VHDL Based Design

Experience with Simulation Debug

Sound Knowledge of Logic Design Principles

Experience writing and using process automation scripts (Unix shell
scripts, Tcl/Perl scripts)

Job Location: Santa Clara, California, USA

Submit your resumes in plain text to:

http://www.tharas.com

Tharas Systems Inc.,
2518 Mission College Blvd, Suite 101, Santa Clara, CA 95054