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VHDL to schematic conversion

 
 
khansa
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      04-06-2005
Please mention a tool that can accepts VHDL code and converts it into
a circuit schematic(preferably at the register transfer level or gate
level). Does ORCAD have such an option?
 
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Jonathan Bromley
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      04-06-2005
On 6 Apr 2005 08:39:19 -0700, http://www.velocityreviews.com/forums/(E-Mail Removed) (khansa) wrote:

>Please mention a tool that can accepts VHDL code and converts it into
>a circuit schematic(preferably at the register transfer level or gate
>level). Does ORCAD have such an option?


Any decent VHDL synthesis tool (Design Compiler from Synopsys,
Leonardo Spectrum or Precision Synthesis from Mentor,
Synplify from Synplicity, etc etc) will do this. Don't expect
it to be free though.

Altera Quartus and Xilinx XST are synthesis tools from the
device vendors that can be obtained free, at least in some
configurations. I'm not sure whether they offer schematic
viewers in the free versions, but they can definitely
create netlist outputs.
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Jonathan Bromley, Consultant

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Hans
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      04-06-2005
Hi Khansa,

Mentor Graphics HDL designer has a code-to-graphics option (good for looking
at the hierarchy), for gate level most synthesis tools
(Synplify/Precision/Spectrum) have a RTL/Gatelevel schematic viewer. I am
not sure about Orcad though,

Hans.
www.ht-lab.com

"khansa" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) m...
| Please mention a tool that can accepts VHDL code and converts it into
| a circuit schematic(preferably at the register transfer level or gate
| level). Does ORCAD have such an option?


 
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Hendra
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      04-06-2005
khansa wrote:
> Please mention a tool that can accepts VHDL code and converts it into
> a circuit schematic(preferably at the register transfer level or gate
> level). Does ORCAD have such an option?


Xilinx ISE Webpack, which can be downloaded from Xilinx website, offer
such an option. It's called Schematic Viewer. It's not as good as the
40K dollars Synopsis or Synplicity tool, but it's free.

Hendra

 
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Robert
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      04-07-2005
I assume what you are looking for is a tool that will take RTL and
create a schematic at the RTL level, or at the gate level with a
netlist, without a synthesis step. If you synthesize it, it will look
totally different then a RTL schematic of the same circuit. You can use
the Undertow Suite source code debugging set of software to do this.
This software is also a fraction of the cost of a synthesis tool, and
is very easy to use. The Undertow Suite will display a schematic of
Verilog, VHDL, mixed Verilog and VHDL and SystemVerilog. You can
download this software from www.veritools.com, and get a no cost
license at (E-Mail Removed).

Robert Schopmeyer/Veritools, Inc.


khansa wrote:
> Please mention a tool that can accepts VHDL code and converts it into
> a circuit schematic(preferably at the register transfer level or gate
> level). Does ORCAD have such an option?


 
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Engineering Guy
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      04-13-2005
khansa wrote:

> Please mention a tool that can accepts VHDL code and converts it into
> a circuit schematic(preferably at the register transfer level or gate
> level). Does ORCAD have such an option?


Aldec's Active-HDL has a Code2Graphics converter that works quite well
with VHDL and Verilog. It generates either block diagrams for structure
and finite state machine bubble diagrams for certain code templates.
It can convert to a block diagram virtually anything since it allows for
behavioral (concurrent assignments and processes) blocks in the document...

EG
 
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