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VHDL - PSL stmts in VHDL: how to describe asynchronous dependencies?

 
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Old 04-05-2005, 05:10 PM   #1
Default PSL stmts in VHDL: how to describe asynchronous dependencies?


Hi,

could someone post some piece of code illustrating the use of the PSL
syntax to describe asynchronous dependencies between signals? Any
attempt to describe async. dependencies and to veriy the assertions w/
ModelSim failed miserabely w/ the comment that the clock was missing.

Eric


Eric DELAGE
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Old 04-05-2005, 05:27 PM   #2
Jonathan Bromley
 
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Default Re: PSL stmts in VHDL: how to describe asynchronous dependencies?
On Tue, 05 Apr 2005 18:10:32 +0200, Eric DELAGE <"eric UNDERSCORE
delage AT yahoo DOT fr"> wrote:

>could someone post some piece of code illustrating the use of the PSL
>syntax to describe asynchronous dependencies between signals? Any
>attempt to describe async. dependencies and to veriy the assertions w/
>ModelSim failed miserabely w/ the comment that the clock was missing.


PSL properties must be sampled.

Unclocked properties are, in principle, sampled every time the
simulator wakes up - i.e. every active delta. This is of course
impractical. Consequently, all the tools I'm aware of simply
forbid unclocked properties.

You can, of course, have multiple-clocked properties to
represent behaviours that cover more than one clock domain.
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Jonathan Bromley, Consultant

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Jonathan Bromley
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Old 04-06-2005, 06:15 AM   #3
Neo
 
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Default Re: PSL stmts in VHDL: how to describe asynchronous dependencies?
I believe modelsim still dosent support unclocked properties.



Neo
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