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Re: 2 inverters in series

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Jason Zheng <(E-Mail Removed)> wrote in message news:<d2rsvr$ndj$(E-Mail Removed)>...
> Removed) wrote:
> > Hi
> >
> > Is there some trick that your can do so that when assigning 2 inverter
> > in series, that they won't get "optimised" away. I don't know why I
> > need this, but it would be cool to do. Thanks. I know this not really
> > about verilog, but it would be great if I can do it using verilog
> > without using schematics.
> >

> For synplify, I think you need to use "syn_keep" directive on the output
> net to preserve the seemingly redundant logic. There might be use for
> this on some specialty circuits, such as some interfacing logic between
> two clock domains. But other than that, I don't know why you would need it.
> -jz


good post

thank you
May goodness be with you all
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