What to do with "Unconnected output port" warnings?

VHDL arch, clkdll_divide doesn't use all the ports of the CLKDLL
component. For instance, component CLKDLL ports CLK90, CLK180, CLK270,
and CLK2X are not mapped. The XST synthesizer complains about these
being unconnected. Is there some way I can assign these ports (to dead
logic or otherwise) in order to resolve the XST warning messages?
Thanks,
-HT

library ieee;
use ieee.std_logic_1164.all;

entity clkdll_divide is
port (
clk_in : in std_logic;
clk_out : out std_logic
);
end clkdll_divide;


architecture Behavioral of clkdll_divide is

component CLKDLL
generic (CLKDV_DIVIDE : real);
port (
CLKIN, CLKFB, RST : in STD_LOGIC;
CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic
);
end component;

component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;

component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;


signal CLKIN, CLK : std_logic;
signal CLK0, CLKDV : std_logic;
signal gnd, LOCKED : std_logic := '0';


begin

ibufg_1 : IBUFG port map (I => clk_in, O => CLKIN);

clkdll_1 : CLKDLL
generic map (CLKDV_DIVIDE => 2.5) -- for simulation and PAR
port map (CLKIN => CLKIN, CLKFB => CLK, RST => gnd,
CLK0 => CLK0, CLKDV => CLKDV, LOCKED =>
LOCKED);

clk0_bufg_1 : BUFG port map (I => CLK0, O => CLK);
clkdv_bufg_1 : BUFG port map (I => CLKDV, O => clk_out);


end Behavioral;

Analyzing Entity <clkdll_divide> (Architecture <behavioral>).
WARNING:Xst:766 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 49:
Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:766 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 56:
Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 57:
Generating a Black Box for component <BUFG>.
Entity <clkdll_divide> analyzed. Unit <clkdll_divide> generated.

Herb T

Did you try:
either:

component CLKDLL
generic (CLKDV_DIVIDE : real);
port (
CLKIN, CLKFB, RST : in STD_LOGIC;
CLK0, LOCKED : out std_logic
);
end component;


or:

clkdll_1 : CLKDLL
generic map (CLKDV_DIVIDE => 2.5) -- for simulation and PAR
port map (CLKIN => CLKIN, CLKFB => CLK, RST => gnd,
CLK0 => CLK0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLKDV => CLKDV, LOCKED => LOCKED);


Herb T wrote:
> VHDL arch, clkdll_divide doesn't use all the ports of the CLKDLL
> component. For instance, component CLKDLL ports CLK90, CLK180, CLK270,
> and CLK2X are not mapped. The XST synthesizer complains about these
> being unconnected. Is there some way I can assign these ports (to dead
> logic or otherwise) in order to resolve the XST warning messages?
> Thanks,
> -HT
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity clkdll_divide is
> port (
> clk_in : in std_logic;
> clk_out : out std_logic
> );
> end clkdll_divide;
>
>
> architecture Behavioral of clkdll_divide is
>
> component CLKDLL
> generic (CLKDV_DIVIDE : real);
> port (
> CLKIN, CLKFB, RST : in STD_LOGIC;
> CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic
> );
> end component;
>
> component IBUFG
> port (
> I : in std_logic;
> O : out std_logic
> );
> end component;
>
> component BUFG
> port (
> I : in std_logic;
> O : out std_logic
> );
> end component;
>
>
> signal CLKIN, CLK : std_logic;
> signal CLK0, CLKDV : std_logic;
> signal gnd, LOCKED : std_logic := '0';
>
>
> begin
>
> ibufg_1 : IBUFG port map (I => clk_in, O => CLKIN);
>
> clkdll_1 : CLKDLL
> generic map (CLKDV_DIVIDE => 2.5) -- for simulation and PAR
> port map (CLKIN => CLKIN, CLKFB => CLK, RST => gnd,
> CLK0 => CLK0, CLKDV => CLKDV, LOCKED =>
> LOCKED);
>
> clk0_bufg_1 : BUFG port map (I => CLK0, O => CLK);
> clkdv_bufg_1 : BUFG port map (I => CLKDV, O => clk_out);
>
>
> end Behavioral;
>
> Analyzing Entity <clkdll_divide> (Architecture <behavioral>).
> WARNING:Xst:766 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 49:
> Generating a Black Box for component <IBUFG>.
> WARNING:Xst:753 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
> Unconnected output port 'CLK90' of component 'CLKDLL'.
> WARNING:Xst:753 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
> Unconnected output port 'CLK180' of component 'CLKDLL'.
> WARNING:Xst:753 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
> Unconnected output port 'CLK270' of component 'CLKDLL'.
> WARNING:Xst:753 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
> Unconnected output port 'CLK2X' of component 'CLKDLL'.
> WARNING:Xst:766 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 51:
> Generating a Black Box for component <CLKDLL>.
> WARNING:Xst:766 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 56:
> Generating a Black Box for component <BUFG>.
> WARNING:Xst:766 - D:/design/ISE/Tutorial/clkdll_divide.vhd line 57:
> Generating a Black Box for component <BUFG>.
> Entity <clkdll_divide> analyzed. Unit <clkdll_divide> generated.
>

Stephane