VHDL language of choice?

Folks,
I was talking to some electronics buffs on a chat channel, and they
were telling me that only Universities and DOD uses VHDL. I thought it
was hogwash, but wanted to find out if many commercial companies are
using the language earnestly. The resident HDL expert was saying
verilog is the language of choice these days. Is that true? I
personally prefer VHDL because the I already have too many reference
materials on how to use it.
Thanks,
-HT

Herb T

verilog is widely prevalent in asic design world and is the language of
choice. But in FPGA design community both are widely used.

Neo

On 4 Apr 2005 00:14:45 -0700, "Neo" <> wrote:

>verilog is widely prevalent in asic design world and is the language of
>choice. But in FPGA design community both are widely used.

It isn't that simple; there are many serious commercial ASIC/custom
outfits that use VHDL.

Sadly, though, it is true that VHDL simply doesn't seem to have the
momentum that Verilog has. I know that Jim Lewis and all the
great people involved in VHDL-200x are working hard to rectify
that, but in the last analysis the only sensible approach for
an individual engineer is: become bilingual in VHDL and Verilog.
--
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Jonathan Bromley

Herb T wrote:
> Folks,
> I was talking to some electronics buffs on a chat channel, and they
> were telling me that only Universities and DOD uses VHDL. I thought it
> was hogwash, but wanted to find out if many commercial companies are
> using the language earnestly. The resident HDL expert was saying
> verilog is the language of choice these days. Is that true? I
> personally prefer VHDL because the I already have too many reference
> materials on how to use it.

I was somewhat surprised when I received Xilinx EDK, and all the cores
included with it (numbering 50-75 I would say) were written in VHDL. I
was even more surprised when I discovered that all the bit vectors were
written as std_logic_vector(0 to n) (instead of downto)!

Duane Clark

Herb T wrote:


> I was talking to some electronics buffs on a chat channel, and they
> were telling me that only Universities and DOD uses VHDL. I thought it
> was hogwash, but wanted to find out if many commercial companies are
> using the language earnestly. The resident HDL expert was saying
> verilog is the language of choice these days. Is that true? I
> personally prefer VHDL because the I already have too many reference
> materials on how to use it.

Most of the american companies use Verilog while in Europe VHDL is common.

I prefer VHDL, too, because
* it is strongly typed and typing errors, that did not lead to syntax
errors are detected more often
* it avoids all these ugly cases mentioned in "verilog coding styles,
that kill" (Clifford Cummings
http://www.sunburst-design.com/paper...2000SJ_NBA.pdf )
* it protects better from writing to one signal from different processes
* signed / unsigned arithmetics are defined more preceisely (with the
disadvantage of having all these type conversions)
* handling of multi-dimensional vectors is possible and handling of
two-dimensional vectors is much easier
* generic parameters and generate statements are easier to use than
Verilog parameters and defines
* finally: VHDL code it better human-readable - IMHO

Ralf

Ralf Hildebrandt

Herb,
The statistics I heard was that in 2001 VHDL had
60% of the FPGA market. Verilog had 15% of the
FPGA market and the remaining 25% went to other
entry methods. Hence the early FPGA tool development
and FPGA model development favored VHDL.

With the a large portion of the market shifting from
ASIC to FPGA I am sure the market share has changed, but
that does not change the pre-existing intellectual
property for FPGAs being developed in VHDL.

The historic opposite happened with Verilog in the
ASIC market. Verilog was first to have a gate level
netlist, and hence, became a significant solution for
the ASIC market.

All marketing statistics I have seen where the Verilog
crowd claims to have market share are based on EDA tool
sales, where the ASIC tools cost >>> the FPGA tools, and
hence, showed that more $$$ were spent on Verilog tools.
This is a significant measure for EDA tool vendors as it
indicates where there is money to be made. It was never
a measure of users, although some would like to convince
you it is. Because of this, many emphatically believe that
Verilog has a significant lead in user adoption. It is the
difference of looking at numbers rather than looking at data.

There is an on-going revision of VHDL in progress. It is
adding a number of significant features (such as uncostrained
arrays of arrays - very useful in parameterized models),
generics on packages, packages for fixed and floating
point, integration of PSL, and language simplification
(case and if statements). In the area of math, VHDL will
have an advantage over Verilog/System Verilog as they don't
have their own solution for these fixed and floating point.
For more details see the papers page at:
http://www.synthworks.com/papers

In the next revision (immediately following this one) we will
be adding enhanced verification features, similar to what
System Verilog has done (such as constrained random). We will
also be using the new features of the language (specifically
generics on packages) to write packages that implement advanced
verification data structures (such as queues, FIFOS, and
memories).

Best Regards,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~



> Folks,
> I was talking to some electronics buffs on a chat channel, and they
> were telling me that only Universities and DOD uses VHDL. I thought it
> was hogwash, but wanted to find out if many commercial companies are
> using the language earnestly. The resident HDL expert was saying
> verilog is the language of choice these days. Is that true? I
> personally prefer VHDL because the I already have too many reference
> materials on how to use it.
> Thanks,
> -HT
>

Jim Lewis

In article <>,
Jim Lewis <> wrote:
>
>There is an on-going revision of VHDL in progress. It is
>adding a number of significant features (such as uncostrained
>arrays of arrays - very useful in parameterized models),
>generics on packages, packages for fixed and floating
>point, integration of PSL, and language simplification
>(case and if statements). In the area of math, VHDL will
>have an advantage over Verilog/System Verilog as they don't
>have their own solution for these fixed and floating point.
>For more details see the papers page at:
>http://www.synthworks.com/papers
>
>In the next revision (immediately following this one) we will
>be adding enhanced verification features, similar to what
>System Verilog has done (such as constrained random). We will
>also be using the new features of the language (specifically
>generics on packages) to write packages that implement advanced
>verification data structures (such as queues, FIFOS, and
>memories).
>

Any changes planned for the scope of user defined attributes? As in will
they be accessable outside of the package they're defined in? (not being
able to do this now tends to make them not very useful). Allowing user
defined attributes on types to be accessable outside of the package
they're defined in, for example, would seem to move VHDL in a more OO
direction (which should be a good thing

As far as VHDL vs. Verilog popularity goes: comp.lang.vhdl seems to get
consistently more traffic then comp.lang.verilog.

Phil

Phil Tomson

Phil,
If you have a language issue that you think needs to be
addressed, you can submit an enhancement request against
it at:
http://www.eda.org/vasg/bugrep.htm

If you have trouble remembering this, there is a link to
it at:
http://www.eda.org/vhdl-200x/


Best Regards,
Jim


> In article <>,
> Jim Lewis <> wrote:
>
>>There is an on-going revision of VHDL in progress. It is
>>adding a number of significant features (such as uncostrained
>>arrays of arrays - very useful in parameterized models),
>>generics on packages, packages for fixed and floating
>>point, integration of PSL, and language simplification
>>(case and if statements). In the area of math, VHDL will
>>have an advantage over Verilog/System Verilog as they don't
>>have their own solution for these fixed and floating point.
>>For more details see the papers page at:
>>http://www.synthworks.com/papers
>>
>>In the next revision (immediately following this one) we will
>>be adding enhanced verification features, similar to what
>>System Verilog has done (such as constrained random). We will
>>also be using the new features of the language (specifically
>>generics on packages) to write packages that implement advanced
>>verification data structures (such as queues, FIFOS, and
>>memories).
>>
>
>
> Any changes planned for the scope of user defined attributes? As in will
> they be accessable outside of the package they're defined in? (not being
> able to do this now tends to make them not very useful). Allowing user
> defined attributes on types to be accessable outside of the package
> they're defined in, for example, would seem to move VHDL in a more OO
> direction (which should be a good thing
>
> As far as VHDL vs. Verilog popularity goes: comp.lang.vhdl seems to get
> consistently more traffic then comp.lang.verilog.
>
> Phil


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Jim Lewis

Herb T wrote:

> Folks,
> I was talking to some electronics buffs on a chat channel, and they
> were telling me that only Universities and DOD uses VHDL. I thought it
> was hogwash, but wanted to find out if many commercial companies are
> using the language earnestly. The resident HDL expert was saying
> verilog is the language of choice these days. Is that true? I
> personally prefer VHDL because the I already have too many reference
> materials on how to use it.

This is a myth prepuated by some people and companies that typically
have a vested interest in Verilog or system Verilog.

I have real data from Dataquest that says VHDL is about 50/50 with
Verilog. Verilog has the advantage in ASIC space, and VHDL in FPGA
space. Note that there are MANY more FPGAs being designed than ASICs,
however ASICs are worth much more to the EDA companies than FPGAs are.

David Bishop

On Sat, 09 Apr 2005 15:33:53 GMT, David Bishop <>
wrote:

>Herb T wrote:
>
>> Folks,
>> I was talking to some electronics buffs on a chat channel, and they
>> were telling me that only Universities and DOD uses VHDL. I thought it
>> was hogwash, but wanted to find out if many commercial companies are
>> using the language earnestly. The resident HDL expert was saying
>> verilog is the language of choice these days. Is that true? I
>> personally prefer VHDL because the I already have too many reference
>> materials on how to use it.
>
>This is a myth prepuated by some people and companies that typically
>have a vested interest in Verilog or system Verilog.
>
>I have real data from Dataquest that says VHDL is about 50/50 with
>Verilog. Verilog has the advantage in ASIC space, and VHDL in FPGA
>space. Note that there are MANY more FPGAs being designed than ASICs,
>however ASICs are worth much more to the EDA companies than FPGAs are.

I have another piece of real data. If you go to dice and search for
VHDL and Verilog keywords across US and In Bay Area/Silicon Valley
Metro areas, you get almost even numbers in whole US and twice as many
Verilog related jobs in the Bay Area.Monster gives similar results
(320/304 for Verilog/VHDL) if you do a generic search and (140/80 in
Northern California). This seems to correlate with your Dataquest data
as Bay Area is heavily into ASICs and the distribution of FPGAs would
be more even across US.

mk