modelsim - looking at memories

Folks
I was trying to look at an std_logic array in modelsim for a block ram
module that i wrote.I can see the data and address lines wiggling with the
correct test input data from my test bench.however if i see the internal
RAM array all locations come up as "UUUUUUUU".Any ideas why this could be
happening?

thanks

fpgawizz

fpgawizz wrote:

> RAM array all locations come up as "UUUUUUUU".Any ideas why this could be
> happening?

Since a RAM has no reset,
it comes filled with 'U's.
Writing RAM will replace
the 'U's at one location with data.

-- Mike Treseler

Mike Treseler

Mike
I am writing data into this RAM. I have a testbench that writes like 5
data bytes into 5 different locations..I can see the addr and data lines
getting the right data when WE is asserted but inside the array, they all
turn up as "UUUUUUUU"

fpgawizz