xilinx ise doubts

hello

1.
i m using ise 6.3i. i wanted to know if there is a project
such as
A.vhd which contain components a1.vhd a2.vhd a3.vhd
B.vhd
used_package.vhd


a.vhd and b.vhd are independent of each other...

b.vhd is just for testing sub-blocks of a.vhd

without removing b.vhd is it possible to do translate P&R ,pin
assignment etc and download a.vhd project to fpga ??
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2.
i added a library fplib in my project manually by editing project file
and used the library. when i added another library floatlib all the
files from fplib library moved to work .....why ?? though project is
working still fine...i m confused
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3.
in testbench waveform ...i want to extend the "end of testbench"
blue line to 3000 clock cycles. i know it would take me yrs to drag it
ther..is ther any other way out ? for big testbench do i have to
manually write testbench ??
I want to run my testbench for 128*128 cycles to see complete
functioning..
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4.
i m getting the following error whenever i open my
project...project is compiling fine...and modelsim results are as
expected..

Error"
Circular heirarchy reference found. Breaking cycle at module
delay.vhd"

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5.
i m using embedded 18*18 bit multiplier...but i dont know how
many...as ther r just too many blocks. how to find out how much
embedded multipliers are consumed ??
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6.
If after translate and P&R ...i get max. clock freq as 104.23
Mhz...does that mean i can clock my black box at 104Mhz or still less
??




nisheeth

Nisheeth