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Division of an integer by a real number using VHDL

 
 
Doug
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      03-31-2005
Hal is spot on here.

Just multiply by K=0.7352941176. And how do you do that?

One way is to represent K by a 24 bit natural, let's call it Ki where
Ki = (2**24) * k = (2**24) / 1.36 = 12336188 (rounded off).

I will assume your 24 bit number is unsigned, let's call it G. You will
then end up with a 48 bit result for G.
R = G * Ki; -- R is 48 bits, G is 24 bits, and Ki is 24 bits.
G is a 24 bit integer with no fractional part.
Ki is a 24 bit fraction where 0xFFFFFF represents a value very
close to 1.0. Actually it ((2**24)-1)/(2**24) = 0.999999940395

The result, R, is a 48 bit number with 24 bit integer part and 24 bit
fractional part. You can drop the fractional part and retain the
24 MSBs and there you have it.


Doug


"Hal Murray" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> >I am basically trying to divide a 24 bit vector by 1.36.(output result
> >eventually being a bit vector)

>
> One trick is to multiply by the inverse.
>
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genlock
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      03-31-2005
Thankyou everybody,

I think I have got all my questions answered. Am going to try the
methods suggested here and see how it works....

 
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David Bishop
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      04-01-2005
genlock wrote:

> Hi,
>
> Is there a way to divide an integer by a real number(decimal number).
>
> Can we simply use the operator '/' as follows:
> eg: a <= 1234/ 1.36;
> where we define 'a' as an integer.
>
> Are there any specific libraries to be included for such a VHDL design
> file.
>
> If so, should these libraries be included in a particular order?


The fixed point packages can deal with this.

http://www.eda.org/vhdl-200x/vhdl-20...ges/files.html
get "fixed_pkg.vhd" and "fixed_pkg_body.vhd".

Write it this way:

signal b : ufixed (15 downto 0);
signal c : ufixed (0 downto -10);
signal a : ufixed (26 downto -1);
begin
b <= to_ufixed (1234, b'high, b'low);
c <= to_ufixed (1.36, c'high, c'low);
a <= b / c;

Should synthesize OK of your tool can deal with an unsigned divide.
 
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Bert Cuzeau
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      04-01-2005
Who said arithmetic was difficut in an FPGA

It's just an example. It can be further optimized.
It's a parallel full speed solution...

-- Divide a 24 bits unsigned by 1.122
-- Author : Bert Cuzeau
-- not overly optimized (yet under 150 LCs of plain logic)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

-- ---------------------------------------
Entity DIVBYR is -- Divide a 24 bits by 1.122
-- ---------------------------------------
Port ( Clk : In std_logic; -- Main System Clock
Rst : In std_logic; -- Asynchronous reset, active high
D : in unsigned (23 downto 0); -- use std_logic_vector !
Q : out unsigned (23 downto 0) -- use std_logic_vector !
); --
end;

-- ---------------------------------------
Architecture RTL of DIVBYR is
-- ---------------------------------------
begin

process (Rst,Clk)
begin
if Rst='1' then
Q <= (others=>'0');
elsif rising_edge (Clk) then
Q <= to_unsigned( (to_integer(D) * 7301 / 8192 ),24);
end if;
end process;

end RTL;

 
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genlock
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      04-01-2005
Thankyou very much for all the help regarding this topic....

Does anybody have any idea about dithering?

Thanks

 
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Pete Fraser
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      04-01-2005
"genlock" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...

> Does anybody have any idea about dithering?


I have a few. What do you want to do.
If you're worried about dropping bits.
you can add the dropped bits in on the
next sample. That is simple and works well for
video, and probably many other signals.

Ulichney goes into dithering in some detail.

http://www.amazon.com/exec/obidos/tg...books&n=507846


 
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genlock
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      04-02-2005
Yes I am actually truncating a 48 bit value to 24 bits and hence am
losing the last 24 bits information of audio.....

So I would like to do dithering

Thankyou

 
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Pete Fraser
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      04-02-2005
"genlock" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Yes I am actually truncating a 48 bit value to 24 bits and hence am
> losing the last 24 bits information of audio.....
>
> So I would like to do dithering


I'm not an audio guy, but I would have thought
that 24 bits would have been fine.
Can you hear anything more?

Last time I was working on audio was 1976,
and 14 bits was the best we could do.

If you have a dedicated adder at the output
(say 48 bits but that's adding overkill to
overkill) and take the most significant 24 bits out
to go to your dac, you need to take the dropped
(least significant) 24 bits, delay them in a register,
and feed the output of the register, appropriately
sign extended, back to the input of the adder,
where it is summed with the full 48 bits of the
next sample. It will spectrally shape your noise
so it is less objectionable to those with super-human
hearing.


 
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info_
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      04-02-2005
genlock wrote:
> Yes I am actually truncating a 48 bit value to 24 bits and hence am
> losing the last 24 bits information of audio.....


24 bits is already 144 dB !
Are you sure you lose a lot of useful information ?
 
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Dave Higton
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      04-02-2005
In message <(E-Mail Removed) .com>
"genlock" <(E-Mail Removed)> wrote:

> Yes I am actually truncating a 48 bit value to 24 bits and hence am
> losing the last 24 bits information of audio.....
>
> So I would like to do dithering


Whatever ADC you use, or whatever analogue electronics you have in front
of the ADC, does all the dithering you will ever need.

Dave
 
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