If you want to divide a 24 bits by a real (floating point) just with a
/, do you want the synthesizer to work this out, or do you need it only
in a test bench ?
In a test bench, no problem. Just write legal VHDL.
Like :
to_integer(unsigned(Sample)) / 2 (returns an integer) or :
real(to_integer(unsigned(sample))) / 1.122 which returns a real
etc...
unsigned() is a type conversion, to_integer() is a conversion.
For synthesis, the efficient method is different.
For example you could :
(to_integer(unsigned(sample)) * 7301 ) / 8192
Multiplying by a constant is easy to most synthesizers and efficiently
implemented (3 add/sub ?). Dividing by a power of 2 is trivial (no
hardware necessary).
For RTL, the solution is even smaller if you can spread the calculation
over 13 clock cycles (in the case above), so you will only need an
accumulator and a shiftregister.
This problem has a lot of solutions, well documented in many books.
Choose the one best suited to your needs and constraints.
Bert
