Binary division

I am trying to divide a 24 bit binary value by 2,4,8...for which I have
used the following syntax:

sample / "000000000000000000000010"

It keeps showing an error as follows :

/ can not have such operands in this context

Any suggestions welcome.

Thanks

genlock

Did you simply try sample / 2 ????
If sample is signed or unsigned or integer range, it should work.
If not, simply do type conversions.

The "hardware orientated" guys (like me) would probably do a shift right...


genlock wrote:

> I am trying to divide a 24 bit binary value by 2,4,8...for which I have
> used the following syntax:
>
> sample / "000000000000000000000010"
>
> It keeps showing an error as follows :
>
> / can not have such operands in this context
>
> Any suggestions welcome.
>
> Thanks
>

info_

I tried sample / 2 but it keeps showing the same error.....sample is a
24 bit vector.

The point is that I have to divide this bit vector value by 1.122 in
which case , I cannot use a shift right operation.

What kind of type conversions are u referring to?

I tried converting the 24 bit binary to an integer but I need to divide
this integer by the value 1.122.

It shows the same error for using the operator '/'

Any suggestions

Thankyou

genlock

If you want to divide a 24 bits by a real (floating point) just with a
/, do you want the synthesizer to work this out, or do you need it only
in a test bench ?

In a test bench, no problem. Just write legal VHDL.
Like :
to_integer(unsigned(Sample)) / 2 (returns an integer) or :
real(to_integer(unsigned(sample))) / 1.122 which returns a real
etc...
unsigned() is a type conversion, to_integer() is a conversion.

For synthesis, the efficient method is different.
For example you could :
(to_integer(unsigned(sample)) * 7301 ) / 8192
Multiplying by a constant is easy to most synthesizers and efficiently
implemented (3 add/sub ?). Dividing by a power of 2 is trivial (no
hardware necessary).
For RTL, the solution is even smaller if you can spread the calculation
over 13 clock cycles (in the case above), so you will only need an
accumulator and a shiftregister.
This problem has a lot of solutions, well documented in many books.
Choose the one best suited to your needs and constraints.

Bert

Bert Cuzeau

Bert,
Thankyou very much for this technique.

I want the synthesizer to work and it is working when using the '/'
operator with powers of 2.

What library do I need to add in order to use the function: to_integer?
I need to convert the resultant integer back to a bit vector.

I am using the functions conv_integer and conv_std_logic_vector. I have
added the library
ieee.std_logic_signed.vhd for these functions.

Can you explain where I would need an accumulator and shift register...
I am using Xilinx ISE and coding in VHDL....I dont understnad the RTL
part you are talking about...

I am going to try this solution and see how it works....

Thankyou

genlock

It's just an example. It can be further optimized.
It's a parallel full speed solution...

-- Divide a 24 bits unsigned by 1.122
-- Author : Bert Cuzeau
-- not overly optimzed (under 200 LCs)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

-- ---------------------------------------
Entity DIVBYR is -- Divide a 24 bits by 1.122
-- ---------------------------------------
Port ( Clk : In std_logic; -- Main System Clock
Rst : In std_logic; -- Asynchronous reset, active high
D : in unsigned (23 downto 0); -- use std_logic_vector !
Q : out unsigned (23 downto 0) -- use std_logic_vector !
); --
end;

-- ---------------------------------------
Architecture RTL of DIVBYR is
-- ---------------------------------------
begin

process (Rst,Clk)
begin
if Rst='1' then
Q <= (others=>'0');
elsif rising_edge (Clk) then
Q <= to_unsigned( (to_integer(D) * 7301 / 8192 ),24);
end if;
end process;

end RTL;


genlock wrote:

> Bert,
> Thankyou very much for this technique.
>
> I want the synthesizer to work and it is working when using the '/'
> operator with powers of 2.
>
> What library do I need to add in order to use the function: to_integer?
> I need to convert the resultant integer back to a bit vector.
>
> I am using the functions conv_integer and conv_std_logic_vector. I have
> added the library
> ieee.std_logic_signed.vhd for these functions.
>
> Can you explain where I would need an accumulator and shift register...
> I am using Xilinx ISE and coding in VHDL....I dont understnad the RTL
> part you are talking about...
>
> I am going to try this solution and see how it works....
>
> Thankyou
>

info_