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VHDL - Opening two files

 
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Old 03-28-2005, 12:22 AM   #1
Default Opening two files


Modelsim question

Can I open the same input file, twice, simulataneously, for
reading? I have an application where a BMP image
drives the simulation, and the output should be compared
to the same BMP, somewhat delayed.

b r a d @ a i v i s i o n . c o m




Brad Smallridge
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Old 03-28-2005, 11:50 AM   #2
Mohammed A khader
 
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Default Re: Opening two files

Hi Brad,

There is no need to open the same file twice. You read the file
through access variable, So you can have two acess variables pointing
to the same file..

If it is confusing then make a copy of the same file with a different
name and work with it.

-- Mohammed A Khader.


Brad Smallridge wrote:
> Modelsim question
>
> Can I open the same input file, twice, simulataneously, for
> reading? I have an application where a BMP image
> drives the simulation, and the output should be compared
> to the same BMP, somewhat delayed.
>
> b r a d @ a i v i s i o n . c o m




Mohammed A khader
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Old 03-28-2005, 01:38 PM   #3
info_
 
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Default Re: Opening two files
Brad Smallridge wrote:

> Modelsim question
>
> Can I open the same input file, twice, simulataneously, for
> reading? I have an application where a BMP image
> drives the simulation, and the output should be compared
> to the same BMP, somewhat delayed.


Another usual and general solution is to use a behavioral FIFO to compensate for the
latency in the UUT. You stack incoming data and unstack them when data come outs from
the UUT. (and apply the behavioral transformation in between).
But you should be able to open the file in read mode twice.

Bert


info_
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