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VHDL - undeclared loop variable

 
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Old 03-23-2005, 10:35 PM   #1
Default undeclared loop variable


It seems that I can drop this into a testbench without
declaring col as a signal or a variable or anything.
What is vhdl doing with col?

for col in 1 to 16 loop
wait for clkperiod;
end loop;




Brad Smallridge
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Old 03-23-2005, 11:37 PM   #2
Kai Harrekilde-Petersen
 
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Default Re: undeclared loop variable
"Brad Smallridge" <> writes:

> It seems that I can drop this into a testbench without
> declaring col as a signal or a variable or anything.
> What is vhdl doing with col?


VHDL considers the iteration variable to be constant for each pass
through the loop.

Regards,


Kai
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Kai Harrekilde-Petersen
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Old 03-24-2005, 07:30 AM   #3
My Name
 
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Default Re: undeclared loop variable


Brad Smallridge wrote:

> It seems that I can drop this into a testbench without
> declaring col as a signal or a variable or anything.
> What is vhdl doing with col?
>
> for col in 1 to 16 loop
> wait for clkperiod;
> end loop;
>
>



the only potential draw back that I see to this type of a construct is
that you can't reference "col" anywhere outside of the loop


My Name
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Old 03-24-2005, 09:34 AM   #4
Neo
 
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Default Re: undeclared loop variable
The looping index is considered an implicit variable in vhdl and is
local to the for loop.



Neo
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Old 03-24-2005, 09:50 AM   #5
Alan Fitch
 
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Default Re: undeclared loop variable
Neo wrote:
> The looping index is considered an implicit variable in vhdl and is
> local to the for loop.
>


In fact as Kai pointed out, the loop index is a constant.

All that means in practice is that you can't, for instance, do

col := 10;

inside the loop.

regards
Alan

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Alan Fitch
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http://www.doulos.com


Alan Fitch
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Old 03-24-2005, 09:52 AM   #6
Paul Uiterlinden
 
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Default Re: undeclared loop variable
My Name wrote:
>
>> for col in 1 to 16 loop
>> wait for clkperiod;
>> end loop;

>
> the only potential draw back that I see to this type of a construct is
> that you can't reference "col" anywhere outside of the loop


I don't see that as a drawback. What value would you expect "col" to
have outside the loop anyway?

Paul.


Paul Uiterlinden
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Old 03-24-2005, 09:55 AM   #7
Jonathan Bromley
 
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Default Re: undeclared loop variable
On Thu, 24 Mar 2005 00:30:14 -0700, My Name <> wrote:

[VHDL 'for' loop index is an implied constant within the loop...]
>the only potential draw back that I see to this type of a construct is
>that you can't reference "col" anywhere outside of the loop


Can you show me an example of this kind of thing that I could
read and yet still retain my lunch?
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Jonathan Bromley
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Old 03-25-2005, 07:45 PM   #8
Michael
 
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Default Re: undeclared loop variable
Paul Uiterlinden wrote:
> My Name wrote:
>
>>
>>> for col in 1 to 16 loop
>>> wait for clkperiod;
>>> end loop;

>>
>>
>> the only potential draw back that I see to this type of a construct is
>> that you can't reference "col" anywhere outside of the loop

>
>
> I don't see that as a drawback. What value would you expect "col" to
> have outside the loop anyway?
>
> Paul.



well, neither do I really.


Michael
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