Hi,
Im looking for bit of help / advice!!!
Im desining a counter for a device and I am using flip flops to do so. Im
using a d-type flip flop then using that flip flop as a component for
other modules. The problem I am getting is when I use the flip flop as a
module I am not getting the output waveforms I am expecting. In fact Im
getting no waveforms!!
Here is the code for my flip flop:
entity dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end dflipflop;
architecture Behavioral of dflipflop is
begin
process(Clk)
begin
if (Clk'event and Clk = '1') then
Q <= D;
Q_bar <= not(D);
end if;
end process;
end Behavioral;
I then use that code as a component to generate a counter that will divide
by 2, 4, 8, and 16.
For example here is the code for my divide by 2 counter using the above
code as a component:
entity divide_by_two is
Port (Clk : in std_logic;
Clk_out : out std_logic);
end divide_by_two;
architecture Behavioral of divide_by_two is
component dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end component;
signal D : std_logic;
--signal F : std_logic;
begin
uuu: dflipflop port map(D,Clk,Clk_Out,D);
end Behavioral;
The code is compiling fine. After debuging the code I think the problem
is that my Q_bar is being equal to my D instead of the other way around
but I cannot seem to set D equal to Q_bar.
I am hoping that after looking at this for so long that it is in fact a
simple error on my part and any help would be greatly appreciated.
Please contact me at
