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Removing Latches from FSM

 
 
Eric
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      03-18-2005
Hi me again, Im trying to remove latches from my code but im not sure
how, here is a very simple code (only FSM transition process) to show
what im trying to do:

transition : process(rd_en) is

variable a,b : std_logic_vector(1 downto 0);


begin

case state is

when S0 =>

if rd_en = '1' then
a := datain;
Next_state <= S1;
else
Next_state <= S0;
end if;

when S1 =>

if rd_en = '1' then
b := datain;
Next_state <= S2;
else
NExt_state <= S1;
end if;

when S2 =>

dataout <= a & b;
Next_state <= S0;

when Others =>

dataout <= "0000";
a := "00";
b := "00";

end case;
end process;


ok this is a simplified FSM, what im doing is reading from a RAM into
variables.....which i then output to a 4bit dataout. As i understand
latches will be created for a and b, since their values need to be
stored. Am i wrong?
 
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Mohammed A khader
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Posts: n/a
 
      03-18-2005
Hi Eric,

'state' signal is not in your sensitivity list.

if you would like to have combinational logic then assign the
default output values before the case statment.








Eric wrote:
> Hi me again, Im trying to remove latches from my code but im not sure
> how, here is a very simple code (only FSM transition process) to show
> what im trying to do:
>
> transition : process(rd_en) is
>
> variable a,b : std_logic_vector(1 downto 0);
>
>
> begin
>
> case state is
>
> when S0 =>
>
> if rd_en = '1' then
> a := datain;
> Next_state <= S1;
> else
> Next_state <= S0;
> end if;
>
> when S1 =>
>
> if rd_en = '1' then
> b := datain;
> Next_state <= S2;
> else
> NExt_state <= S1;
> end if;
>
> when S2 =>
>
> dataout <= a & b;
> Next_state <= S0;
>
> when Others =>
>
> dataout <= "0000";
> a := "00";
> b := "00";
>
> end case;
> end process;
>
>
> ok this is a simplified FSM, what im doing is reading from a RAM into
> variables.....which i then output to a 4bit dataout. As i understand
> latches will be created for a and b, since their values need to be
> stored. Am i wrong?


 
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Eric
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Posts: n/a
 
      03-18-2005
ok i guess my state machine was over simplyfied. After writing the
signal to the output i have to wait for an acknoledge signal before i
can remove the value from dataout.....if i write a default value of
dataout before the case statement the value will be erased before it
is read?
 
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info_
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Posts: n/a
 
      03-19-2005
Eric wrote:
> Hi me again, Im trying to remove latches from my code but im not sure
> how, here is a very simple code (only FSM transition process) to show
> what im trying to do:
>
> transition : process(rd_en) is
>

etc...

Hi Eric,

Looks like you're trying to describe an _asynchronous_ state machine ?
From your question, it seems also that you want to synthesize it.

I'm afraid this won't work very well.
Designing asynchronous sequential logic is possible, but not
through (usual) synthesis tools.

I'm sure you didn't find this in Peter's book

Your ram is probably synchronous, and if not, it still isn't
a good reason to try and read it asynchronously.

Writing a synchronous solution instead is my recommendation.

 
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info_
Guest
Posts: n/a
 
      03-20-2005
Eric,

I strongly suggest you adopt a one-process synchronous style.
If you're not trying to describe asynchronous sequential logic
(which wouldn't work through synthesis anyway), I think you
would avoid lots of headaches if you reviewed the one-process
style, understand how it works (actions in transitions) and
adopt it.

Describing combinational logic (that works) with a process
is a surprisingly treacherous path !

In you process you violated several rules :

- the sensitivity must be COMPLETE !
This includes signals from the RHS of assignments ("read")
but indeed also signals used in tests ! (if ... case ... etc)
(and also signals that you would assign _and_ read, but
this is really really bad -comb feedback loop-).

- beware of variables ! (in general)
variables for which a path in the code exists where they
are read before being assigned a value means you want
latches (memories). To me, it seems you did this in S2 !
You are explicitly wrinting asynchronous sequential logic
for a and b.
Variables have a local scope and are often a challenge
when debugging. Variables are not meant to model a net
(signals are), though they can.

A few simple _RTL_ rules that I recommend :

* stay away from variables when you don't really need them.
Use signals instead.
(indeed, it's the opposite rule in simulation/behavioral code)
If you use variable, even in synchronous processes, you must
understand & remember the memory inference rule (see above).

* You need to understand how sequential signal assignments
work in VHDL, understand the simulation cycle and what delta
are about in particular.
This know-how is mandatory to write VHDL that works.

* Stay away from processes to describe combinational logic !
Simple combinatinal logic can be expressed in continuous assignments
with the advantage of a "free" (and accurate) sensitivity list.
But it is usually easier to describe the comb logic together
with the FlipFlop(s) that follow it.

* Never _ever_ forget to resynchronize the external signals (inputs) !
When they are used in FSMs, they will make it fail with
the weirdest symptoms !
(and, no : the issue is not metastability. The failure can
occur without any timing violation).

There are indeed many more recommendations... I wrote a "VHDL coding
style" document as a base for designers who have none yet, but
these few rules above would probably decrease by two the volume
of reported "problems".

We -indeed- use FSMs a lot in all our designs.
You can take a look at our free IPs at
http://www.alse-fr.com/english/ips.html
No surprise : you'll see a lot of one-process State machines

Hope it will help you a bit,

Bert


Eric wrote:
> Hi me again, Im trying to remove latches from my code but im not sure
> how, here is a very simple code (only FSM transition process) to show
> what im trying to do:
>
> transition : process(rd_en) is
>
> variable a,b : std_logic_vector(1 downto 0);
>
>
> begin
>
> case state is
>
> when S0 =>
>
> if rd_en = '1' then
> a := datain;
> Next_state <= S1;
> else
> Next_state <= S0;
> end if;
>
> when S1 =>
>
> if rd_en = '1' then
> b := datain;
> Next_state <= S2;
> else
> NExt_state <= S1;
> end if;
>
> when S2 =>
>
> dataout <= a & b;
> Next_state <= S0;
>
> when Others =>
>
> dataout <= "0000";
> a := "00";
> b := "00";
>
> end case;
> end process;
>
>
> ok this is a simplified FSM, what im doing is reading from a RAM into
> variables.....which i then output to a 4bit dataout. As i understand
> latches will be created for a and b, since their values need to be
> stored. Am i wrong?


 
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purush
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Posts: n/a
 
      03-21-2005
if u don't mind can i have that document of yours"VHDL coding
style"...i need them very badly as even we have no proper guide
lines...send it across if thatz not proprietary

 
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Bert Cuzeau
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Posts: n/a
 
      03-24-2005
purush wrote:
> if u don't mind can i have that document of yours"VHDL coding
> style"...i need them very badly as even we have no proper guide
> lines...send it across if thatz not proprietary
>

See post about the subject
(it's at http://www.alse-fr.com/archive/VHDL_Coding_eng.pdf)

 
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