Velocity Reviews > VHDL > Over-Sampling

# Over-Sampling

ALuPin
Guest
Posts: n/a

 03-11-2005
Hello @ VHDL people out there,

I have the following problem. Maybe someone of you has experienced the same:

The signal "input_data" comes from a 12MHz clock domain.
Now I want to sample that signal that way that I generate one sample-enable
which is close to the center position of the bits.
One possibility to do so is to use a over-sampling clock, let us assume
48MHz.

When stepping to the signal processing of my design
I see that the sampled signal which is in the 48MHz clock domain now
has to be synchronized into a 90MHz clock domain.

So my idea was to sample the "input_data" with a sample-enable directly
in the 90MHz clock domain.

The problem: 90 is not a multiple of 12.
Is there a possibility to sample the 12MHz signal right in the center ?

When using 48MHz sample clock I use a simple counter with which I can
define the position of the sampling point.

Any suggestions are appriciated.

Rgds
Andre

Peter Hermansson
Guest
Posts: n/a

 03-11-2005
http://www.velocityreviews.com/forums/(E-Mail Removed) (ALuPin) wrote in message news:<(E-Mail Removed). com>...
> Hello @ VHDL people out there,
>
> I have the following problem. Maybe someone of you has experienced the same:
>
> The signal "input_data" comes from a 12MHz clock domain.
> Now I want to sample that signal that way that I generate one sample-enable
> which is close to the center position of the bits.
> One possibility to do so is to use a over-sampling clock, let us assume
> 48MHz.
>
>
> The problem: 90 is not a multiple of 12.
> Is there a possibility to sample the 12MHz signal right in the center ?
>

Hi,

90/12 = 7.5 and fractional division may be performed by dividing by 7
one cycle and 8 the next. If the jitter is acceptable, the resulting
divisor is 7.5.

/Peter

Falk Brunner
Guest
Posts: n/a

 03-11-2005

"ALuPin" <(E-Mail Removed)> schrieb im Newsbeitrag
news:(E-Mail Removed) om...

> Hello @ VHDL people out there,
>
> I have the following problem. Maybe someone of you has experienced the

same:
>
> The signal "input_data" comes from a 12MHz clock domain.
> Now I want to sample that signal that way that I generate one

sample-enable
> which is close to the center position of the bits.
> One possibility to do so is to use a over-sampling clock, let us assume
> 48MHz.

USB??

> So my idea was to sample the "input_data" with a sample-enable directly
> in the 90MHz clock domain.
>
> The problem: 90 is not a multiple of 12.
> Is there a possibility to sample the 12MHz signal right in the center ?

Sure, just take some smart FSM to track the 12 MHz data signal clocking. Or
easier, us a asynchronous FIFO.

Regards
Falk

Kolja Sulimma
Guest
Posts: n/a

 03-11-2005

ALuPin wrote:

> The problem: 90 is not a multiple of 12.
> Is there a possibility to sample the 12MHz signal right in the center ?

Sample with a 180MHz clock.

Kolja Sulimma

John_H
Guest
Posts: n/a

 03-11-2005
No matter what approach you use, the only way to sample "exaclty" in the
middle of the data bit is to have an analog PLL for clock recovery. If you
use an unrelated 48 MHz clock, you can be off by +/- 1/8 bit period if you
use an ideal digitally phase locked loop for "effective" clock recovery. A
faster sampling rate would provide better than the cumulative 1/4 period.

"ALuPin" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) om...
> Hello @ VHDL people out there,
>
> I have the following problem. Maybe someone of you has experienced the

same:
>
> The signal "input_data" comes from a 12MHz clock domain.
> Now I want to sample that signal that way that I generate one

sample-enable
> which is close to the center position of the bits.
> One possibility to do so is to use a over-sampling clock, let us assume
> 48MHz.
>
> When stepping to the signal processing of my design
> I see that the sampled signal which is in the 48MHz clock domain now
> has to be synchronized into a 90MHz clock domain.
>
> So my idea was to sample the "input_data" with a sample-enable directly
> in the 90MHz clock domain.
>
> The problem: 90 is not a multiple of 12.
> Is there a possibility to sample the 12MHz signal right in the center ?
>
> When using 48MHz sample clock I use a simple counter with which I can
> define the position of the sampling point.
>
> Any suggestions are appriciated.
>
> Rgds
> Andre

jtw
Guest
Posts: n/a

 03-12-2005
Or, you may be able to use both edges of the clock to produce a de-facto 180
MHz. Use with care.

Jason

"Peter Hermansson" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) om...
> (E-Mail Removed) (ALuPin) wrote in message
> news:<(E-Mail Removed). com>...
>> Hello @ VHDL people out there,
>>
>> I have the following problem. Maybe someone of you has experienced the
>> same:
>>
>> The signal "input_data" comes from a 12MHz clock domain.
>> Now I want to sample that signal that way that I generate one
>> sample-enable
>> which is close to the center position of the bits.
>> One possibility to do so is to use a over-sampling clock, let us assume
>> 48MHz.
>>
>>
>> The problem: 90 is not a multiple of 12.
>> Is there a possibility to sample the 12MHz signal right in the center ?
>>

>
> Hi,
>
> 90/12 = 7.5 and fractional division may be performed by dividing by 7
> one cycle and 8 the next. If the jitter is acceptable, the resulting
> divisor is 7.5.
>
> /Peter