Or, you may be able to use both edges of the clock to produce a de-facto 180

MHz. Use with care.

Jason

"Peter Hermansson" <(E-Mail Removed)> wrote in message

news:(E-Mail Removed) om...

> (E-Mail Removed) (ALuPin) wrote in message

> news:<(E-Mail Removed). com>...

>> Hello @ VHDL people out there,

>>

>> I have the following problem. Maybe someone of you has experienced the

>> same:

>>

>> The signal "input_data" comes from a 12MHz clock domain.

>> Now I want to sample that signal that way that I generate one

>> sample-enable

>> which is close to the center position of the bits.

>> One possibility to do so is to use a over-sampling clock, let us assume

>> 48MHz.

>>

>>

>> The problem: 90 is not a multiple of 12.

>> Is there a possibility to sample the 12MHz signal right in the center ?

>>

>

> Hi,

>

> 90/12 = 7.5 and fractional division may be performed by dividing by 7

> one cycle and 8 the next. If the jitter is acceptable, the resulting

> divisor is 7.5.

>

> /Peter