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generic std_logic_vector & range

 
 
KCL
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      03-02-2005
Hi

Is it possible to declare a std_logic_vector of size that is log2(A) with A
a generic??
I was thinking of doing something like a range signal but doesn't work, does
anyoneone have any idea without using integer/natural signal??

Thanks

Alexis


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ztest is
generic(
A : integer :=132
);
port(
rst : in std_logic;
clk : in std_logic;
data_out : out std_logic_vector( range A downto 0 )
);
end ztest;

architecture Behavioral of ztest is
signal cpt: std_logic_vector range (A downto 0);
signal
begin

process (clk)
begin
if rising_edge(clk) then
if rst ='1' then
cpt <= (others=>'0');
else
if unsigned(cpt)=(A) then
cpt <= (others=>'0');
else
cpt <= std_logic_vector(unsigned(cpt)+1);
end if;
end if;
end if
end process;

data_out <= cpt;

end Behavioral;


 
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Egbert Molenkamp
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Posts: n/a
 
      03-03-2005
"KCL" <(E-Mail Removed)> wrote in message
news:422626f5$0$11713$(E-Mail Removed)...
> Hi
>
> Is it possible to declare a std_logic_vector of size that is log2(A) with
> A a generic??
> I was thinking of doing something like a range signal but doesn't work,
> does anyoneone have any idea without using integer/natural signal??
>
> Thanks
>
> Alexis
>
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use ieee.NUMERIC_STD.all;
>
> entity ztest is
> generic(
> A : integer :=132
> );
> port(
> rst : in std_logic;
> clk : in std_logic;
> data_out : out std_logic_vector( range A downto 0 )
> );
> end ztest;
>


Place the following functions in a package, say 'support' and it will work.
data_out : out std_logic_vector( log2(A) .... )

The solution with the WHILE is general solution. Most of the synthesis tools
I used supported that.
The solution with the for loop is not that nice but more synthesis tools
support that in stead of the WHILE solution.
Notice that the log2 checks if N is a power of 2 and ceil_log2 returns the
'round up' value.

Egbert Molenkamp

function log2 (N : positive) return natural is -- N should be power of
two.
variable res : integer;
begin
res := ceil_log2(N);
assert 2**res=N report "N is not a power of 2" severity note;
return res;
end log2;

-- function ceil_log2 (N : positive) return natural is
-- variable tmp, res : integer;
-- begin
-- tmp:=1 ; res:=0;
-- while tmp < N loop
-- tmp:=tmp*2;
-- res:=res+1;
-- end loop;
-- return res;
-- end ceil_log2;

-- *SDC: This version of ceil_log2 uses a for loop instead of a while loop
function ceil_log2 (N : positive) return natural is
variable tmp, res : integer;
variable out_of_range : boolean;
begin
tmp:=1 ; res:=0;
out_of_range:=true;
for i in 0 to 10 loop
if tmp < N then
tmp:=tmp*2;
else
res:=i;
out_of_range:=false;
exit;
end if;
end loop;
assert not out_of_range report "increase upper bound of for loop in
function ceil_log2 (package <the package name>)" severity error;
return res;
end ceil_log2;


 
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