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EC/ECP Map Problem

 
 
=?ISO-8859-1?Q?Andr=E9s?=
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      02-25-2005
Hi FPGA people,

I am trying to map my VHDL design on a Lattice-EC FPGA. (LFEC20E-5F672CES)

The following error warning occurs:

*********************************
Map checkpoint failed.
Design's logic delay (97 percent of total delay)
exceeds the 60 percent limit set in the map checkpoint options
*********************************
Process Stopped.

Done: failed with exit code: 0001.


Unfortunately there is no direct "double click" HELP for this error
message and I could not find any hint in the HELP menu.

Has someone of you any idea what this message could mean ?


Thank you in advance.

Rgds
Andrés
 
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cristian
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      02-28-2005
Andres,

The ispLEVER software has an option that allow you to stop/continue
witht the map process depending on the porcentage of the delay that you
set.
That is, if you go to Tools-> Timing Checkpoint Options, the Timing
Checkpoint Options window will come up. There you can set the Estimated
Logic Delay that you will allow and then you have to tell the tool
whether to Stop or Continue when that number is violated. The 'Before
Route' is related to the Map process.

rgds

cristian

 
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=?ISO-8859-1?Q?Andr=E9s?=
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      03-01-2005
cristian wrote:
> Andres,
>
> The ispLEVER software has an option that allow you to stop/continue
> witht the map process depending on the porcentage of the delay that you
> set.
> That is, if you go to Tools-> Timing Checkpoint Options, the Timing
> Checkpoint Options window will come up. There you can set the Estimated
> Logic Delay that you will allow and then you have to tell the tool
> whether to Stop or Continue when that number is violated. The 'Before
> Route' is related to the Map process.
>
> rgds
>
> cristian
>


Hi Cristian,

thank you for your answer.

When I step through the design flow I perform MAP DESIGN. Having a look
at the Map Trace Report I can see the following lines in it:

----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "ts_clk" 133.330000 MHz ; | 133.333 MHz| 136.724 MHz| 0
| | |
FREQUENCY NET "ts_clk_90" 133.330000 | | |
MHz ; | 133.333 MHz| 826.446 MHz| 0
| | |
FREQUENCY NET "ts_wrclock" 66.660000 | | |
MHz ; | 66.662 MHz| 246.002 MHz| 0
| | |
----------------------------------------------------------------------------

When I go further in the design flow can try to perform MAP TIMING
CHECKPOINT I get the error message I stated before:

*********************************
Map checkpoint failed.
Design's logic delay (97 percent of total delay)
exceeds the 60 percent limit set in the map checkpoint options
*********************************
Process Stopped.

Done: failed with exit code: 0001.

I mean 97 percent would mean that there is some logic part which blows
up in a very heavy way. Why does the MAP TRACE Report not
find that fault ?

Rgds
Andrés
 
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