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Hi,

i'm trying to compile this vhdl file using MAX+PLUSII but I keep
having these errors:

Node '|fortuit_module_lpm_ff:FORTUIT1|227.IN1' missing source
Node '|fortuit_module_lpm_ff:FORTUIT2|227.IN1' missing source

it's comming from a component I made and compiled perfectly
(fortuit_module_lpm_ff)

here's the beginning of my code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fortuit_mult_module_lpm_ff IS

PORT
(
iStrobe_A : IN STD_LOGIC;
iStrobe_B : IN STD_LOGIC;
iData_A : IN STD_LOGIC_VECTOR(12 downto 0);
iData_B : IN STD_LOGIC_VECTOR(12 downto 0);
iClk : IN STD_LOGIC;
iClear : IN STD_LOGIC;

oFlagFortuit : OUT STD_LOGIC;
oData_A : OUT STD_LOGIC_VECTOR(12 downto 0);
oData_B : OUT STD_LOGIC_VECTOR(12 downto 0)
);

END fortuit_mult_module_lpm_ff;

ARCHITECTURE BEHAVIORAL OF fortuit_mult_module_lpm_ff IS

component fortuit_module_lpm_ff
port (
iStrobe_A : IN STD_LOGIC;
iStrobe_B : IN STD_LOGIC;
iData_A : IN STD_LOGIC_VECTOR(12 downto 0);
iData_B : IN STD_LOGIC_VECTOR(12 downto 0);
iClk : IN STD_LOGIC;
iClear : IN STD_LOGIC;

oFlagFortuit : OUT STD_LOGIC;
oData_A : OUT STD_LOGIC_VECTOR(12 downto 0);
oData_B : OUT STD_LOGIC_VECTOR(12 downto 0)
);
end component;

COMPONENT LATCH
PORT (d : IN STD_LOGIC;
ena: IN STD_LOGIC;
q : OUT STD_LOGIC);
END COMPONENT;

SIGNAL sSelectBlk : STD_LOGIC;
SIGNAL sMuxSelect : STD_LOGIC;
SIGNAL sFlagFortuit : STD_LOGIC;

SIGNAL sStrobe_A1 : STD_LOGIC;
SIGNAL sFlagFort1 : STD_LOGIC;
SIGNAL sData_A1 : STD_LOGIC_VECTOR(12 downto 0);
SIGNAL sData_B1 : STD_LOGIC_VECTOR(12 downto 0);
SIGNAL sClear1 : STD_LOGIC;

SIGNAL sStrobe_A2 : STD_LOGIC;
SIGNAL sFlagFort2 : STD_LOGIC;
SIGNAL sData_A2 : STD_LOGIC_VECTOR(12 downto 0);
SIGNAL sData_B2 : STD_LOGIC_VECTOR(12 downto 0);
SIGNAL sClear2 : STD_LOGIC;

BEGIN

FORTUIT1:fortuit_module_lpm_ff port map(sStrobe_A1, iStrobe_B,
iData_A, iData_B, iClk, sClear1, sFlagFort1, sData_A1, sData_B1);
FORTUIT2:fortuit_module_lpm_ff port map(sStrobe_A2, iStrobe_B,
iData_A, iData_B, iClk, sClear2, sFlagFort2, sData_A2, sData_B2);


I carefully assigned an entry to every input/output of both components
but it doesn't work.

Anyone has an idea on what could be the problem?
I can show you the rest of the file or the component's code if you
need...

thanks
Vince

Vince Perron wrote:

> Hi,
>
> i'm trying to compile this vhdl file using MAX+PLUSII but I keep
> having these errors:
>
> Node '|fortuit_module_lpm_ff:FORTUIT1|227.IN1' missing source
> Node '|fortuit_module_lpm_ff:FORTUIT2|227.IN1' missing source
>
> it's comming from a component I made and compiled perfectly
> (fortuit_module_lpm_ff)
>
> here's the beginning of my code:
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
>
> ENTITY fortuit_mult_module_lpm_ff IS
>
> PORT
> (
> iStrobe_A : IN STD_LOGIC;
> iStrobe_B : IN STD_LOGIC;
> iData_A : IN STD_LOGIC_VECTOR(12 downto 0);
> iData_B : IN STD_LOGIC_VECTOR(12 downto 0);
> iClk : IN STD_LOGIC;
> iClear : IN STD_LOGIC;
>
> oFlagFortuit : OUT STD_LOGIC;
> oData_A : OUT STD_LOGIC_VECTOR(12 downto 0);
> oData_B : OUT STD_LOGIC_VECTOR(12 downto 0)
> );
>
> END fortuit_mult_module_lpm_ff;
>
> ARCHITECTURE BEHAVIORAL OF fortuit_mult_module_lpm_ff IS
>
> component fortuit_module_lpm_ff
> port (
> iStrobe_A : IN STD_LOGIC;
> iStrobe_B : IN STD_LOGIC;
> iData_A : IN STD_LOGIC_VECTOR(12 downto 0);
> iData_B : IN STD_LOGIC_VECTOR(12 downto 0);
> iClk : IN STD_LOGIC;
> iClear : IN STD_LOGIC;
>
> oFlagFortuit : OUT STD_LOGIC;
> oData_A : OUT STD_LOGIC_VECTOR(12 downto 0);
> oData_B : OUT STD_LOGIC_VECTOR(12 downto 0)
> );
> end component;
>
> COMPONENT LATCH
> PORT (d : IN STD_LOGIC;
> ena: IN STD_LOGIC;
> q : OUT STD_LOGIC);
> END COMPONENT;
>
> SIGNAL sSelectBlk : STD_LOGIC;
> SIGNAL sMuxSelect : STD_LOGIC;
> SIGNAL sFlagFortuit : STD_LOGIC;
>
> SIGNAL sStrobe_A1 : STD_LOGIC;
> SIGNAL sFlagFort1 : STD_LOGIC;
> SIGNAL sData_A1 : STD_LOGIC_VECTOR(12 downto 0);
> SIGNAL sData_B1 : STD_LOGIC_VECTOR(12 downto 0);
> SIGNAL sClear1 : STD_LOGIC;
>
> SIGNAL sStrobe_A2 : STD_LOGIC;
> SIGNAL sFlagFort2 : STD_LOGIC;
> SIGNAL sData_A2 : STD_LOGIC_VECTOR(12 downto 0);
> SIGNAL sData_B2 : STD_LOGIC_VECTOR(12 downto 0);
> SIGNAL sClear2 : STD_LOGIC;
>
> BEGIN
>
> FORTUIT1:fortuit_module_lpm_ff port map(sStrobe_A1, iStrobe_B,
> iData_A, iData_B, iClk, sClear1, sFlagFort1, sData_A1, sData_B1);
> FORTUIT2:fortuit_module_lpm_ff port map(sStrobe_A2, iStrobe_B,
> iData_A, iData_B, iClk, sClear2, sFlagFort2, sData_A2, sData_B2);
>
>
> I carefully assigned an entry to every input/output of both components
> but it doesn't work.
>
> Anyone has an idea on what could be the problem?
> I can show you the rest of the file or the component's code if you
> need...

In my experience, most synthesizers do not support positional
association for instantiations. Try using named association
(portname->signalname in your portmap. It is also MUCH easier to read
when you're debugging.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

Tim Hubberstey <> wrote in message news:<QKpTd.4412$TB.398@edtnps84>...
> In my experience, most synthesizers do not support positional
> association for instantiations. Try using named association
> (portname->signalname in your portmap. It is also MUCH easier to read
> when you're debugging.

I already tried and it doesn't make any difference. Positional
association is supported because I used it for another component and
it worked perfectly.

Thx anyway Tim,

Vince