Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Pin declarations in EC/ECP FPGAs

Reply
Thread Tools

Pin declarations in EC/ECP FPGAs

 
 
ALuPin
Guest
Posts: n/a
 
      03-02-2005
>That basically is just an ouptut that
>is connected to the global reset signal. That is the way to activate
>the reset after configuration.



Hi Cristian,

when simulating I can see in Modelsim that
the component gsr has only inputs:

Name Value Kind Mode
timingcheckson false Generic In
xon false Generic In
msgon false Generic In
instancepath gsr Generic In
gsr 1 Signal In

So how can I connect gsr to the global reset signal
if gsr is an input ?

Rgds
Andrés
 
Reply With Quote
 
 
 
 
cristian
Guest
Posts: n/a
 
      03-11-2005

ALuPin wrote:
> >That basically is just an ouptut that
> >is connected to the global reset signal. That is the way to activate
> >the reset after configuration.

>
>
> Hi Cristian,
>
> when simulating I can see in Modelsim that
> the component gsr has only inputs:
>
> Name Value Kind Mode
> timingcheckson false Generic In
> xon false Generic In
> msgon false Generic In
> instancepath gsr Generic In
> gsr 1 Signal In
>
> So how can I connect gsr to the global reset signal
> if gsr is an input ?
>
> Rgds
> Andrés



Andres,
The GSR is a component that has an input: the signal that will be used
as global reset. You have to supply that input to the GSR component.
During power up all the components tied to that global reset signal
will be reset/set by the GSR component. The GSR component does not have
a 'visible' output signal, but it has one that set/reset all the FF
controled by the global reset signal.
When simulating your design the simulator should show the FF reset/set
after a short time if you are using the GSR component and before
activating your global reset signal.

rgds.

cristian

 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Modify 24 pin PSU connector to 20 pin JM Computer Information 7 11-28-2006 09:55 PM
Bug in DDR template in Lattice FPGAs ? ALuPin VHDL 8 04-28-2005 07:22 AM
How To Synchronize FPGAs Leroy Tanner VHDL 4 09-24-2004 02:17 PM
tools for FPGAs Jluis VHDL 1 06-18-2004 01:31 PM
FPGAs and Linux Neil Zanella VHDL 1 11-18-2003 12:01 PM



Advertisments