Hi,

Simply

b <= unsigned(a);

http://www.velocityreviews.com/forums/(E-Mail Removed) wrote in message news:<cv52k2$ai5$(E-Mail Removed)>...

> I need to convert a std_logic_vector into an unsigned, and I am surprised

> that this seems not to work.

>

> signal a : std_logic_vector ( 5 downto 0 );

> signal b : unsigned ( 5 downto 0 );

>

> I tried:

>

> b <= a;

> b <= to_unsigned ( a, 6 );

> b <= conv_unsigned ( a, 6 );

>

> with used libs (several combinations commented in or out):

> library ieee;

> use ieee.std_logic_1164.all;

> use ieee.std_logic_arith.all; --do not use both ???

> --use ieee.numeric_bit.all;

> use ieee.numeric_std.all;

> --use ieee.std_logic_unsigned.all;

>

> all with Xilinx web pack 6.2.03i.

> Syntax check claims in different ways, usually ...can not have such

> operands in this context.

>

> What am I doing wrong?

>

> Klaus

>

> BTW conversion from unsigned to std_logic_vector works.