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testbench procedure trouble

Peter Hermansson
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Mike Treseler <(E-Mail Removed)> wrote in message news:<(E-Mail Removed)>...
> Toby wrote:
> > Can somebody either post, or tell me EXACTLY where to find a nice, BIG,
> > COMPLETE, good, testbench example with all this stuff you guys are
> > talking about? Several examples would be even better, but all this
> > stuff you guys are showing me is just pieces, and I'm having a little
> > trouble seeing the overall picture of a good testbench design. Thanks!

> My comments are incomplete, but here you go:
> -- Mike Treseler


A very interesting example. There are a lot of things that are
unfamiliar to me even if I have used VHDL for some years. Could you
please explain the "init_out_variables" procedure that executes on
every clock edge? Whats its purpose? Would it be possible for you
(dont want to waste your time...) to explain more from basic, the
structure of this example?

Regards, Peter
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Yes that is a very interesting example. It has completely changed the
way I write testbenches, and I suspect it will also change the way I
write my VHDL design files. Thank you Mike! Does anyone else have any
COMPLETE testbench examples they can show me? I just love examples!
Thanks again Mike, your the best!


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Mike Treseler
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it prevents double output registers.
I will fill in the info files next week.

-- Mike Treseler

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