On Thu, 10 Feb 2005 16:32:56 +0100, Ronan Guivarc'h
<> wrote:
>i discover something strange today concerning signal assignment.
You have discovered the defined behaviour of inertial
assignment in VHDL.
>what is the physical explanation ?
That's the way VHDL defines it. Future assignments *to the same
value* do not overwrite earlier assignments. It is done that
way to provide an approximation to the behaviour of RC delays.
> My example has perhaps no physical reality ?
Indeed it does not; but neither has anything else in a digital
simulator

The rules are set up to make typical examples
behave in a physically sensible way, without the need for
full analogue simulation.
For some styles of modelling you may find it's better to use
transport delay:
y <= TRANSPORT newvalue after T;
This adds a scheduled assignment after time T without
affecting existing scheduled assignments.
--
Jonathan Bromley, Consultant
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