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Query about MOD operator for synthesis
Posts: n/a
Hello All,

Below mentioned is a code for simple counter, I was not able to
synthesize the same because of mod operator. Since the implementation
available for modulus are by powers of 2. In my case the mod values
aren't power's of 2.

How can i resolve this problem ?


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cpx_controller is

clk : in std_logic;
reset : in std_logic;
en_counter : in std_logic;
count_approx : out std_logic_vector(17 downto 0);
count_detail : out std_logic_vector (17 downto 0)
end cpx_controller;

architecture cpx_control of cpx_controller is

signal count_appr : natural;
signal count_deta : natural;
signal count_mod : natural;
signal incrementer : natural;

constant row_size : natural := 288;
constant col_size : natural := 176;
constant col_offset : natural := 50688;


counter_check: process(clk,reset,en_counter)


if (reset='0' or en_counter = '0') then
count_mod <= 0;
elsif (clk'event and clk='1') then
if (en_counter = '1') then
count_mod <= (count_mod+1) mod 176;
end if;
end if;
end process counter_check;

counter_approx: process(clk,reset)


if (reset='0') then
incrementer<= 0;
elsif (clk'event and clk = '1')then
if (count_mod = 175) then
incrementer <= (incrementer+1) mod 288;
end if;
end if;

end process counter_approx;

count_appr <= incrementer + count_mod*row_size;
count_deta <= col_offset+count_appr;

count_approx <= std_logic_vector((to_unsigned(count_appr,1));
count_detail <= std_logic_vector((to_unsigned(count_deta,1));

end architecture cpx_control;


Thanks in advance,

Reply With Quote
Allan Herriman
Posts: n/a
On 7 Feb 2005 00:32:33 -0800, Removed) wrote:

It appears that you just want a counter with a certain terminal count
rather than a general mod operation.

Try changing:

count_mod <= (count_mod+1) mod 176;


if count_mod < 175 then
count_mod <= count_mod+1;
count_mod <= 0;
end if;

This should do the same thing, assuming that count_mod never exceeds

BTW, avoid using type 'natural' for synthesis. This may produce a 32
bit value, unless the synthesiser is particularly clever. It is
better to use a constrained range, or perhaps an unsigned of
appropriate width.

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