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Synthesis problem

 
 
VHDL_lover
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      01-30-2005
I am getting errors in simulation of post synthesis VHDL file.

errors are like
----dffr is not a component declaration.
-----Statement cannot be labeled. etc for all primitives using in the
flattened file

i mapped adk library also and the condition is same.
any help will be really great.

Thanks


 
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Neo
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      01-31-2005
I think there are scan inertion cells in you netlist for which a
library has to be attached.

 
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VHDL_lover
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      02-08-2005
Thanks for reply.

what is scan inertion cells and which library need to be attached to
remove it?


 
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