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I was reading a paper on "LOW-POWER DIGIT-SERIAL MULTIPLIER"
And I came accross a problem of how they measured the power dissipated
in the Multiplier which they have designed.
It said on a paper that,they are using HEAT:Hierarchical Energy
Analysis
Tool,which is based on SPICE.
I discussed with my Prof about this,but he adviced me not to use a
HSPICE
(which is available in our Uni) because a Multiplier is too big a
circuit
to use HSPICE.
My question is how to Am I going to measure power dissipated in a
digital circuit(in this case a Multiplier)

Thanks in advance,
Chris

Christopher Denis wrote:
> I was reading a paper on "LOW-POWER DIGIT-SERIAL MULTIPLIER"
> And I came accross a problem of how they measured the power dissipated
> in the Multiplier which they have designed.
> It said on a paper that,they are using HEAT:Hierarchical Energy
> Analysis
> Tool,which is based on SPICE.
> I discussed with my Prof about this,but he adviced me not to use a
> HSPICE
> (which is available in our Uni) because a Multiplier is too big a
> circuit
> to use HSPICE.
> My question is how to Am I going to measure power dissipated in a
> digital circuit(in this case a Multiplier)

It depends. If the multiplier is serially than you can give HSPICE a
try because the number of transistors is quite low.

Otherwise there are other SPICE variants suitable for simulations of a
very large number of MOSFETs.



--
Bernd

Hi,

You can use Mach PA for power analysis in digital circuit,this is a
mentor graphics tool which takes .sp netlist as its input.
This .sp netlist u can extract either using Hpisce or going though some
sequence of synthesis .
Let me know if you have done coding in vhdl or verilog.

Bernd and VHDL-Lover,

Thanks for your replies.
The circuit ia a digit-serial.

I will look for this Mach PA tool and see how it can help me.
Thanks again,
Chris

Christopher Denis wrote:


> I was reading a paper on "LOW-POWER DIGIT-SERIAL MULTIPLIER"
> And I came accross a problem of how they measured the power dissipated
> in the Multiplier which they have designed.
> It said on a paper that,they are using HEAT:Hierarchical Energy
> Analysis
> Tool,which is based on SPICE.
> I discussed with my Prof about this,but he adviced me not to use a
> HSPICE
> (which is available in our Uni) because a Multiplier is too big a
> circuit
> to use HSPICE.

Well, I have simulated several 16x16 bit Booth-encoded parallel
multipliers (signed-digit, carry-save) with Spectre on an Ultra Sparc
with 300MHz. Run-time for 100 pseudo-random multiplications was around 4
to 8 hours.
(If you are interested in the results - I hade a paper on the ICM 2004
with this topic. I can provide the lecture
http://www.ralf-hildebrandt.de/icm20...dt_lecture.pdf
but as IEEE owns the copyright you have to mail me, if you want to have
the paper.)


> My question is how to Am I going to measure power dissipated in a
> digital circuit(in this case a Multiplier)

At the moment I am working on a transition-based energy estimation
during VHDL simulation. Two ideas came up: Using the input capacitances
of the gates for energy estimation or using pre-computed energy-amounts.
Both ideas have limitations.
As you are more interested in (now) usable possibilities, I can not
recommend one of the at the moment. I am working on it to make it
better.

Ralf