Guard

Hi,

A newbie question: what does "guard" mean in VHDL? Can anybody kindly
give me one example?

Kuan

Kuan Zhou

Probably you can find a little bit more at this location
http://www.acc-eda.com/vhdlref/refgu...res/blocks.htm

Its interesting if a signal if all drivers to a signal are disconnected.
What should be the value of that signal?
Therefore the a signal declaration can be declared as:

signal myobject1 : std_logic REGISTER;
signal myobject1 : std_logic BUS;

In case myobject1 it not driven anymore it remembers its last value.
In case myobject2 is not driven anymore the resolution functions determines
the value.
see more on this at:
http://www-asim.lip6.fr/recherche/al...ubset/vbe.html

Egbert Molenkamp


"Kuan Zhou" <> wrote in message
news h.edu...
> Hi,
>
> A newbie question: what does "guard" mean in VHDL? Can anybody kindly
> give me one example?
>
> Kuan

Egbert Molenkamp

guard is the implicit signal created when you declare a block with a
guard expression. guard expressions are used to control operation of
guarded signal assignments.
ex:
guard_ex: block (value = '1') is
begin
---
signal_a <= guarded (x and y);
---
end block;
here signal_a is a guarded signal evaluated when guard is true ie, when
value='1'.

-Neo

zingafriend@yahoo.com

On Mon, 24 Jan 2005 00:41:42 -0500, Kuan Zhou <>
wrote:

>Hi,
>
> A newbie question: what does "guard" mean in VHDL? Can anybody kindly
>give me one example?

Given that you say you're a newbie, perhaps a better answer would be:

Guard is a keyword you won't ever use in synthesisable code, and
probably won't use in your testbench either.

Regards,
Allan

Allan Herriman