Blocks vs. Entities?

Hi,

I am doing a project in VHDL and one of my VHDL references is "The VHDL
Cookbook", by Peter J. Ashden (available online somewhere in postscript/PDF).

In Chapter 3.2.2, it discusses using blocks within the architecture
declaration to hierarchialize the design. I have not seen references to using
blocks within the architecture in other guides, HOWTO's or manuals: is this
supported in both '87 and '93 VHDL standards?

My main question is this: why would one choose to use blocks instead of using
entities/components? Is there some advantage and/or difference between them
or is it purely the choice of the designer?

gth_n0_spam_orpe@ee.ryerson.ca

Yes, blocks are standard and work as advertised
to allow signals, functions, etc to be declared with
scope limited to the block. Blocks are used
"under to hood" to make component instances work.
However, I have yet to find a good, direct use
for blocks in fpga design or simulation.

One intriguing feature is the idea of adding
a port map around a process (or set of processes)
to make inputs and outputs explicit between
multiple processes. However, my attempts to do this
added confusion rather than clarity to my code.
Today, I prefer to use design entities with
one or two large synchronous processes.

The downside to blocks is that they are no more
reusable or testable than any other parallel statement.
-- Mike Treseler

Mike Treseler