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Re: Is there an elegant way to set an unsigned vector to 1

 
 
Jan De Ceuster
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      01-11-2005
> I'm probably missing something, but I have a vector such as:
>
> signal counter : unsigned(7 downto 0);
>
> and want to set it to and integer (say 1). I have lots of cumbersome
> ways to do it:
>
> counter <= "00000001"; -- Lot's of writing and difficult to maintain.
>
> or
>
> counter <= (others => '0');
> counter(0) <= '1'; -- Not very elegant
> -- Does not work well other integers.
>
> and of course:
>
> counter <= unsigned(1);
>
> What I would really like to do is overload assignment "<=" so I could
> just write:
>
> counter <= 1; -- My idea of elegant
>
> but I don't think VHDL allows that since "<=" is also "less than or
> equal to".
>
> It would be nice if VHDL had a "just copy the damn bits" assignment
> operator, maybe call it "<-", but as far as I know it does not. As near
> as I can tell, the vast majority of so-called conversion functions are
> really just copying bits anyway.
>
> Ok, not the most interesting problem in the world, but VHDL type
> conversion can be an awful pain at times.


well, there are a few sollutions.
use the IEEE.std_logic_arith package and do
counter <= conv_std_logic_vector(1,counter'high-counter'low+1);

or use the IEEE.numeric package (but you'll have to look that one up)
with a similar conversion function.

or write the number in hex format:
counter <= X"01";

a 'clean' sollution to write certain bits:
counter <= (0 => '1', others => '0');

kind regards,
Jan

PS I'm not posting in newsgroups from this email address...
 
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Nicolas Matringe
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      01-12-2005
Jan De Ceuster a écrit :
>
> well, there are a few sollutions.
> use the IEEE.std_logic_arith package and do
> counter <= conv_std_logic_vector(1,counter'high-counter'low+1);
>
> or use the IEEE.numeric package (but you'll have to look that one up)
> with a similar conversion function.


Hello
I'd use the numeric_std package:
counter <= std_logic_vector(to_unsigned(n, counter'length));
(if you declare counter as unsigned instead of std_logic_vector you can
just write counter <= to_unsigned(n, counter'length);
It's still a little cumbersome though.
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Jonathan Bromley
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      01-12-2005
On Wed, 12 Jan 2005 00:31:40 +0100, Jan De Ceuster
<(E-Mail Removed)> wrote:

>> I have a vector such as:
>>
>> signal counter : unsigned(7 downto 0);
>>
>> and want to set it to and integer (say 1). I have lots of cumbersome
>> ways to do it:

[snip]
>>
>> What I would really like to do is overload assignment "<=" so I could
>> just write:
>>
>> counter <= 1; -- My idea of elegant
>>
>> but I don't think VHDL allows that


No, there's no overloading of assignment. A fine opportunity for
religious warfare.

>> It would be nice if VHDL had a "just copy the damn bits" assignment
>> operator, maybe call it "<-",


You're entitled to your own opinion

>> Ok, not the most interesting problem in the world, but VHDL type
>> conversion can be an awful pain at times.


I think it's quite interesting; this kind of thing can make
or break the readability/maintainability of a piece of code.

Don't forget functions and procedures.

procedure Just_Copy_The_Damn_Bits_As_Unsigned_Binary (
signal S: out std_logic_vector;
N: in natural ) is
begin
S <= std_logic_vector ( to_unsigned ( N, S'length ) );
end;
...
JCTDBAUB ( counter , 1 ); -- Maintainable, clear, short

It is left as a trivial exercise for the reader to invent
a better name than JCTDBAUB for that procedure.

If you have a commonly-used subtype, it can be clearer to
use a function...

subtype Machine_Word is std_logic_vector(15 downto 0);
function to_Word ( N: in natural ) is
begin
return std_logic_vector (
to_unsigned ( N, Machine_Word'length ) );
end;
...
counter <= to_Word(1);

All these points are simple and obvious, but easy to
forget in the maelstrom of coding a significant design.
My golden rule is: as soon as I write a fragment of code
for the second time, it's a good moment to write a subprogram.

~~~~~~~~~~ end of sensible advice : start of rant ~~~~~~~~~~~

None of this alters the fact that the lack of assignment
overloading is a sad omission from VHDL. Obviously it's
made more difficult by the existence of two assignment
operators := and <= , but it seems to me that you don't
ever want to change the semantics of signal updating;
therefore, overloading := would be sufficient if you
accept that signal assignment is effectively a variable
assignment, to a hidden temporary variable of the same
subtype as the signal, followed by an update of the
signal using the value held in the hidden variable.

Fixed point arithmetic is an obvious example of a
situation where the lack of assignment overloading
is pretty much disastrous:

variable I: unsigned_fixed(3 downto 0); -- 4-bit integer
variable F: unsigned_fixed(-1 downto -4); -- 4-bit fraction
...
I := F; -- Ha ha, you inadvertently multiplied it by 16
-- and there's nothing the compiler can do to stop you!
--
Jonathan Bromley, Consultant

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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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Kai Harrekilde-Petersen
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      01-12-2005
Nicolas Matringe <(E-Mail Removed)> writes:

> Jan De Ceuster a écrit :
>> well, there are a few sollutions.
>> use the IEEE.std_logic_arith package and do
>> counter <= conv_std_logic_vector(1,counter'high-counter'low+1);
>> or use the IEEE.numeric package (but you'll have to look that one
>> up) with a similar conversion function.

>
> Hello
> I'd use the numeric_std package:
> counter <= std_logic_vector(to_unsigned(n, counter'length));
> (if you declare counter as unsigned instead of std_logic_vector you
> can just write counter <= to_unsigned(n, counter'length);
> It's still a little cumbersome though.


We have defined a bunch of central type-conversion functions that cut
this lexical crap to the minimum.

In our environment, I'd write

counter <= to_uns(1, counter'length);

We have similar to_XXX() functions that cover 99% of the conversions
needed between simple types, e.g. to_slv(), to_sl(), to_bool(),
to_int(), etc.

Having a central package that does this allows everyone to benefit
from this, and ensure that noone uses a "home-grown" conversion
function that has a synthesis issue.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
 
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Stefan Oedenkoven
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      01-12-2005
First thinks about this elegant ideas

a) Is it necessary to begin with one? Just start counting at zero.
b) Is it necessary to use vectors? Use integers.

regards,
Stefan


 
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Thomas Stanka
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      01-13-2005
Jan De Ceuster <(E-Mail Removed)> wrote:
> or use the IEEE.numeric package (but you'll have to look that one up)
> with a similar conversion function.
>
> or write the number in hex format:
> counter <= X"01";


This should do only in VHDL 93 (and newer), but seems to be the best
sollution.

If the task is done for fixed numbers it could be usefull declaring
constants (maybe in a package once for ever).

CONSTANT ONE:std_ulogic_vector(7 donwto 0):="00000001";
.....
counter<=ONE;

bye Thomas
 
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