RAM problem on FPGA

Hello

Currently I am implementing my own IP which I wanna add to the FSL of the
Microblaze soft processor. But unfortunately I have problems with the RAM I
programmed. Although it is fully synthesizeable it doesnt work the way I
want it to on the FPGA. In the simulation it looks good to me, so probably
there is some syntax I use which causes problems on the FPGA. Here is the
VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------
-- START: Memory
-------------------------------------------------------------------
entity memory is
generic (width : integer);
port (clk : in std_ulogic;
rst : in std_ulogic;
data_in : in std_ulogic_vector(31 downto 0);
wr_addr: in std_ulogic_vector(7 downto 0);
wr : in std_ulogic;
rd1_addr :in std_ulogic_vector(7 downto 0);
rd1 : in std_ulogic;
data1_outut std_ulogic_vector(31 downto 0)
);
end memory;

architecture rtl of memory is

type reg_type is array (0 to 3) of std_ulogic_vector(31 downto 0);
signal reg_file : reg_type;

begin

write : process(clk,rst,data_in,wr_addr,wr)
variable x_int : integer;
begin
if rst = '1' then
reg_file(0) <= (others => '0');
reg_file(1) <= (others => '0');
reg_file(2) <= (others => '0');
reg_file(3) <= (others => '0');
x_int:=0;
else
if clk'event and clk = '1' then
x_int:=to_integer(unsigned(wr_addr));
if wr = '1' then
reg_file(x_int) <= data_in;
end if;
end if;
end if;
end process;

read1 : process(clk,rst,rd1_addr,rd1)
variable x_int : integer;
begin
if rst = '1' then
data1_out <= (others => '0');
else
if clk'event and clk = '1' then
x_int:=to_integer(unsigned(rd1_addr));
if rd1 = '1' then
data1_out <= reg_file(x_int);
end if;
end if;
end if;
end process;

end rtl;
-------------------------------------------------------------------
-- END: Memory
-------------------------------------------------------------------
I use the Xilinx ML300 Board as FPGA, would be very thankful if somebody
could point out the problem!

Philipp

Philipp Grabher

Philipp Grabher wrote:

> Currently I am implementing my own IP

Really?

> which I wanna add to the FSL of the
> Microblaze soft processor. But unfortunately I have problems with the RAM I
> programmed. Although it is fully synthesizeable it doesnt work the way I
> want it to on the FPGA. In the simulation it looks good to me, so probably
> there is some syntax I use which causes problems on the FPGA.

This design has already been critiqued
elsewhere in this newsgroup.

-- Mike Treseler

Mike Treseler