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VHDL - Simulation Problem

 
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Old 01-09-2005, 04:10 PM   #1
Default Simulation Problem


Hello all,
I have designed an advanced arithemetic unit (+ - / * sqrt) using both
vhdl and schematics with xilinx 6.3SP2. I have simulated the design
using Modelsim 5.8c XE. The results was satisfying for behavioural
simulation but not ok with place nad route or post map simulation (the
output is invariant ="0000" all the time".
So any one could help me?



mgonullu
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Old 01-09-2005, 05:49 PM   #2
Mike Treseler
 
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Default Re: Simulation Problem
mgonullu wrote:

> The results was satisfying for behavioural
> simulation but not ok with place nad route or post map simulation (the
> output is invariant ="0000" all the time".


Consider posting your behavioural code as is, for comments.
Consider writing a vhdl-only version that infers
the vendor-specific portions of your design.

-- Mike Treseler


Mike Treseler
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