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VHDL - not synthesizable code fragment... error appears at bitstream generation

 
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Old 01-03-2005, 07:46 PM   #1
Default not synthesizable code fragment... error appears at bitstream generation


hi ng,
i get the following error-message during "Programming File Generation":

ERROR:Bitgen:145 - Pin M6 is a persistent pin, but a component exists in
it's
IOB. Please rerun par with the persistent pins prohibited from use.
ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.
Error: bitgen failed
Reason:
Process "Programming File Generation Report" did not complete.

Here is the evil code fragment:

pIR : process (CLK, Reset)
begin
if Reset = '0' then
Pending <= '0';
elsif CLK'event and CLK = '1' then
if IRQ = '1' then
Pending <= '1';
elsif Clear = '1' then -- when i remove "elsif-clause" it
generates the bitstream without an error
Pending <= '0'; -- (synthesizing without errors with AND
without the "elsif-clause")
end if;
end if;
end process;


Anyone have an idea? We have ISE 6.2.03 here and i don't use an ucf-file
which assign Pin M6 to the design. An i can't find this PAR Option in the
PAR-Contextmenu.

thanks,
Stefan




Stefan Oedenkoven
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Old 01-04-2005, 07:22 AM   #2
zinga
 
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Default Re: not synthesizable code fragment... error appears at bitstream ge
There is nothing wrong with the code. The error must be due to some other
reason.



zinga
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