![]() |
|
|
|||||||
![]() |
VHDL - not synthesizable code fragment... error appears at bitstream generation |
|
|
Thread Tools | Search this Thread |
|
|
#1 |
|
hi ng,
i get the following error-message during "Programming File Generation": ERROR:Bitgen:145 - Pin M6 is a persistent pin, but a component exists in it's IOB. Please rerun par with the persistent pins prohibited from use. ERROR:Bitgen:157 - Bitgen will terminate because of the above errors. Error: bitgen failed Reason: Process "Programming File Generation Report" did not complete. Here is the evil code fragment: pIR : process (CLK, Reset) begin if Reset = '0' then Pending <= '0'; elsif CLK'event and CLK = '1' then if IRQ = '1' then Pending <= '1'; elsif Clear = '1' then -- when i remove "elsif-clause" it generates the bitstream without an error Pending <= '0'; -- (synthesizing without errors with AND without the "elsif-clause") end if; end if; end process; Anyone have an idea? We have ISE 6.2.03 here and i don't use an ucf-file which assign Pin M6 to the design. An i can't find this PAR Option in the PAR-Contextmenu. thanks, Stefan Stefan Oedenkoven |
|
|
|
|
#2 |
|
Posts: n/a
|
There is nothing wrong with the code. The error must be due to some other
reason. zinga |
|
![]() |
| Thread Tools | Search this Thread |
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| problem with code for random number generation | sandeep_sp7 | Hardware | 0 | 04-12-2007 04:59 PM |