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Problems with SRAM controller

 
 
bittor
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      12-22-2004
Hello,
I must do a symple controller for SRAM in VHDL. I must write datas and
after read these datas. I have problems with bidirectional port. Someone
has a similar design or an idea for doing this?
Thanks

 
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usrdr@yahoo.co.uk
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      12-23-2004
You can three registers such as Data_in, Data_out and Data. Then you
must use tri-state

Data <= Data_out when RamW = '1' else (others => 'Z' );
Data_in <= Data when RamR = '1' else (others => '0');

 
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bittor
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      12-23-2004
Thanks usrdr,
That's what I've done and now all is running well.
Happy new year!!

 
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