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vhdl 200x status?

 
 
tkvhdl@gmail.com
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Posts: n/a
 
      04-29-2006
Does anyone know the status of VHDL 200x?
When it might be completed?
Has SystemVerilog killed off interest or is it still on track?

 
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Jim Lewis
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Posts: n/a
 
      04-29-2006
VHDL-200X work was taken over by Accellera and
there will be an approved Accellera draft of VHDL
at or just after DAC in July 2006. This work
adopts the majority of the VHDL-200X-FT plus
additional proposals put forward by the Accellera
VHDL TC.

To find out more, you can join the Accellera TC (either
as a member or not) and get access to the current
status. There are links to Accellera VHDL TC through
http://www.eda.org/vasg

This draft is the first in a series of revisions.
Following this draft there are proposals for adding
constrained random, oo, and interfaces as well as
a DPI (direct programming interface).

Best Regards,
Jim Lewis
IEEE VASG Chair


> Does anyone know the status of VHDL 200x?
> When it might be completed?
> Has SystemVerilog killed off interest or is it still on track?

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
 
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Hans
Guest
Posts: n/a
 
      04-29-2006
> Has SystemVerilog killed off interest

I believe this is happening, look at the amount of effort that EDA companies
like Mentor is putting into SystemVerilog (and a bit in SystemC). The
momentum of SystemVerilog is now so large that I wonder if companies can be
steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
Accellera doesn't produce something in say the next 2 years than IMHO VHDL
is dead which is a real shame since I prefer it over Verilog.

Hans
www.ht-lab.com

"(E-Mail Removed)" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Does anyone know the status of VHDL 200x?
> When it might be completed?
> Has SystemVerilog killed off interest or is it still on track?
>




 
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Phil Tomson
Guest
Posts: n/a
 
      04-29-2006
In article <FtF4g.1342$(E-Mail Removed)>,
Hans <(E-Mail Removed)> wrote:
>> Has SystemVerilog killed off interest

>
>I believe this is happening, look at the amount of effort that EDA companies
>like Mentor is putting into SystemVerilog (and a bit in SystemC). The
>momentum of SystemVerilog is now so large that I wonder if companies can be
>steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
>Accellera doesn't produce something in say the next 2 years than IMHO VHDL
>is dead which is a real shame since I prefer it over Verilog.
>


You're probably right. What exactly is Accellera's incentive to produce
a VHDL200x spec?
From their website:
"Accellera was formed in 2000 through the unification of Open Verilog
International and VHDL International to focus on identifying new
standards, development of standards and formats, and to foster the
adoption of new methodologies."

There's a SystemVerilog logo on their home page but I don't see anything
about VHDL200x. They even let you download the SystemVerilog3.1a LRM -
that's nice.

Are (were) there many language syntax changes proposed for VHDL200x? Or
was it mostly new packages? It seems like if it's the latter that the
community might be able to drive this (more like what happens in the open
source world). It's too bad that this all seems to be held hostage by a
single company... at least that's how it seems, any other takes on this?

Phil
 
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Jim Lewis
Guest
Posts: n/a
 
      04-30-2006
In their dream world, we would all switch to SystemVerilog.
No kidding about the marketing effort - this is a no brainer.
If one can convince the VHDL market to switch to SV, at a
minimum they will have to upgrade to enhanced licenses and
this means good revenue. Going further if you can also
convince VHDL users from your competitor that your tool is
better and they will switch. Even thinking about this makes
my eyes see $$$$ and I am not a marketing person

As for delivery from Accellera VHDL TC, DAC of 2006 (July)
is the required delivery date. Accellera is a different
model of working than IEEE. We have until 1 month before DAC to
deliver a standard that is approved by the Accellera VHDL
TC to the Accellera board. The development process has been
to prioritize items and work them through the process of
adding them to the LRM. What is done and approved 1 month
before DAC gets delivered. So the delivery date is set in
stone - the number of new features is negotiable, however,
at this point it looks like we are on track to deliver
what was started by VHDL-200X-FT plus numerous additional
enhancements.

BTW, if you are doing fixed and floating point math, the
Accellera VHDL-2006 adds fixed and floating point
math packages to the language. This is something that
you will not find in SystemVerilog.


Going further, there is also a working plan to start
immediately on the next revision. This revision will
include enhanced verification features such as constrained
random, OO, coverage, interfaces, and a direct programming
interface (DPI). It is at this phase where we will have
the same verification features that SV has. If we can do
this and maintain the clean language design currently
enjoyed by VHDL, then I think we will have a clearly
superior solution.


There is another key difference in the Accellera developement
process that means you will see vendors implementing new
features sooner. In Accellera, proposals are ranked by the
user community. As a result, vendors know that these are
features their user community wants. This is much different
from having a benevolent expert develop a feature only to
learn it does not solve the problems users are having
and as a result, any investment made in implementing the
feature was wasted since the feature was unused.

Rather than judging Accellera by its current pro SystemVerilog
front door, hold your judgement for DAC this year. When
they approve the Accellera VHDL-2006, then you know
that they are truely a multi-language organization.

I have to say, I had concerns about the pro SystemVerilog
stance of Accellera. However, I am impressed both with
the development process and with the effort put forward
by the VHDL technical committee to get this revision done.
Personally I have been putting in around 10 hours per week
on this effort a good portion of this time in meetings,
and I have been skipping half of the meetings.

Best Regards,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~







>>Has SystemVerilog killed off interest

>
>
> I believe this is happening, look at the amount of effort that EDA companies
> like Mentor is putting into SystemVerilog (and a bit in SystemC). The
> momentum of SystemVerilog is now so large that I wonder if companies can be
> steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
> Accellera doesn't produce something in say the next 2 years than IMHO VHDL
> is dead which is a real shame since I prefer it over Verilog.
>
> Hans
> www.ht-lab.com
>
> "(E-Mail Removed)" <(E-Mail Removed)> wrote in message
> news:(E-Mail Removed) oups.com...
>
>>Does anyone know the status of VHDL 200x?
>>When it might be completed?
>>Has SystemVerilog killed off interest or is it still on track?
>>

>
>

 
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Jim Lewis
Guest
Posts: n/a
 
      04-30-2006
Phil,
Before you make a judgement like this, I would encourage
you to open the door and take a look inside and see what
the Accellera VHDL TC is doing. In fact, since you did
make an uninformed comment, you owe it to those of us
who have been putting a great deal of "sweat" equity into
this project.

You do not need to join Accellera to join the Accellera
VHDL TC. You only need to register with Accellera. Note
that you do need to join Accellera however to have
full voting rights.

To register with Accellera, goto:
http://www.accellera.org/activities/vhdl/

On the line that states the following, press "click here"
"If you are not an Accellera member and would like to
join this group, _click here_ to contact us."

In the comments field say:
I would like to sign up for the Accellera VHDL TC


Note that there are also other groups that under the VHDL TC that you
may wish to join (requirements group, extensions group, review group,
and LRM group).

Send the form to: Lynn Horobin, Administration

---------------------------

Once you have joined the Accellera VHDL TC, go to the following
page and login:
http://www.accellera.org/apps/org/wo.../documents.php


To find out the current status of the effort, download the
document: Requirements Status
The latest one I looked at resolves to: RequirementsStatus_25Apr2006.xls
If you look at the statistics in this file, there are 123 approved
enhancements for this revision and 110 of them have approved
LRM edits.

Keep in mind, the main reason we miss requirements in language
design is because either people fail to submit them or people
who are interested in them fail to participate.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

> In article <FtF4g.1342$(E-Mail Removed)>,
> Hans <(E-Mail Removed)> wrote:
>
>>>Has SystemVerilog killed off interest

>>
>>I believe this is happening, look at the amount of effort that EDA companies
>>like Mentor is putting into SystemVerilog (and a bit in SystemC). The
>>momentum of SystemVerilog is now so large that I wonder if companies can be
>>steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
>>Accellera doesn't produce something in say the next 2 years than IMHO VHDL
>>is dead which is a real shame since I prefer it over Verilog.
>>

>
>
> You're probably right. What exactly is Accellera's incentive to produce
> a VHDL200x spec?
> From their website:
> "Accellera was formed in 2000 through the unification of Open Verilog
> International and VHDL International to focus on identifying new
> standards, development of standards and formats, and to foster the
> adoption of new methodologies."
>
> There's a SystemVerilog logo on their home page but I don't see anything
> about VHDL200x. They even let you download the SystemVerilog3.1a LRM -
> that's nice.
>
> Are (were) there many language syntax changes proposed for VHDL200x? Or
> was it mostly new packages? It seems like if it's the latter that the
> community might be able to drive this (more like what happens in the open
> source world). It's too bad that this all seems to be held hostage by a
> single company... at least that's how it seems, any other takes on this?
>
> Phil


 
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Phil Tomson
Guest
Posts: n/a
 
      05-01-2006
In article <(E-Mail Removed)>,
Jim Lewis <(E-Mail Removed)> wrote:
>In their dream world, we would all switch to SystemVerilog.
>No kidding about the marketing effort - this is a no brainer.
>If one can convince the VHDL market to switch to SV, at a
>minimum they will have to upgrade to enhanced licenses and
>this means good revenue. Going further if you can also
>convince VHDL users from your competitor that your tool is
>better and they will switch. Even thinking about this makes
>my eyes see $$$$ and I am not a marketing person
>


This is partly why I asked the question about incentives.
What is Accellera's business model? Apparently they get revenue from dues
paid by member companies (EDA companies). Are there other revenue
streams?

>
>BTW, if you are doing fixed and floating point math, the
>Accellera VHDL-2006 adds fixed and floating point
>math packages to the language. This is something that
>you will not find in SystemVerilog.


Lots of us are eagerly awaiting this. However, even now the proposed
fixed point packages are available and have been for a couple of years,
right? Mostly they work great, however they have not worked with the
Xilinx ISE/xst tools because they do not support negative indices (perhaps
this has changed with ISE 8.1; I have not tried it).

>
>
>Going further, there is also a working plan to start
>immediately on the next revision. This revision will
>include enhanced verification features such as constrained
>random, OO, coverage, interfaces, and a direct programming
>interface (DPI). It is at this phase where we will have
>the same verification features that SV has. If we can do
>this and maintain the clean language design currently
>enjoyed by VHDL, then I think we will have a clearly
>superior solution.


Lots of great stuff there to be sure.

>
>
>There is another key difference in the Accellera developement
>process that means you will see vendors implementing new
>features sooner. In Accellera, proposals are ranked by the
>user community. As a result, vendors know that these are
>features their user community wants. This is much different
>from having a benevolent expert develop a feature only to
>learn it does not solve the problems users are having
>and as a result, any investment made in implementing the
>feature was wasted since the feature was unused.
>
>Rather than judging Accellera by its current pro SystemVerilog
>front door, hold your judgement for DAC this year. When
>they approve the Accellera VHDL-2006, then you know
>that they are truely a multi-language organization.
>
>I have to say, I had concerns about the pro SystemVerilog
>stance of Accellera. However, I am impressed both with
>the development process and with the effort put forward
>by the VHDL technical committee to get this revision done.
>Personally I have been putting in around 10 hours per week
>on this effort a good portion of this time in meetings,
>and I have been skipping half of the meetings.
>


Thanks for all the hard work.



Phil
 
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Phil Tomson
Guest
Posts: n/a
 
      05-01-2006
In article <(E-Mail Removed)>,
Jim Lewis <(E-Mail Removed)> wrote:
>Phil,
>Before you make a judgement like this, I would encourage
>you to open the door and take a look inside and see what
>the Accellera VHDL TC is doing. In fact, since you did
>make an uninformed comment, you owe it to those of us
>who have been putting a great deal of "sweat" equity into
>this project.


Sorry, didn't mean to seem to call anyone's hard work into question.
I thought that my comments were pretty tame, actually: basically just
asked the question "what's in it for Accellera?". Even
in your next reply after this one you mentioned that you yourself were
wary about Accellera's seeming focus on SystemVerilog. A quick glance at
their web page and it's pretty easy to come up with the impression that
they're working on System Verilog. Sure if you dig deeper you can find
that there is a VHDL TC. Maybe they could also have something like "We're
the company working on the VHDL 200x spec - coming soon!" or some such. I
think a lot of people are probably still under the impression that the
IEEE was working on the VHDL 200x spec.

I think part of what makes people wonder is that it's kind of hard to
figure out what kind of 'animal' Accellera is. Is it an EDA company
(apparently not, they don't seem to make any tools of their own). Is it a
standardization committee? (well, it's apparently
a for-profit company). What exactly is Accellera and where does their
revenue come from? (seems to come from membership dues paid by EDA
companies). Now, perhaps Accellera's VHDL 200x efforts are preferrable to
the way that these sorts of things used to be done (in IEEE
standardization committees). We'll find out.


>
>You do not need to join Accellera to join the Accellera
>VHDL TC. You only need to register with Accellera. Note
>that you do need to join Accellera however to have
>full voting rights.
>


From the Accellera blurb on membership:
"Annual corporate membership dues are $15,000 per year, while Associate
membership is $5,000 per year."
So basically that limits voting influence to the big-boys. Most of us see
that as saying: "this is an exclusive club and we don't want any riff-raff
hanging around". Those of us from more of an open-source orientation have
a hard time relating. Even small commercial startup EDA companies might
not have the resources to become members.


>To register with Accellera, goto:
> http://www.accellera.org/activities/vhdl/
>
>On the line that states the following, press "click here"
> "If you are not an Accellera member and would like to
> join this group, _click here_ to contact us."


But if membership has it's priviledges, what exactly can one do if one is
not a member but has 'joined the group'?

>
>In the comments field say:
>I would like to sign up for the Accellera VHDL TC
>
>
>Note that there are also other groups that under the VHDL TC that you
>may wish to join (requirements group, extensions group, review group,
>and LRM group).
>
>Send the form to: Lynn Horobin, Administration
>
>---------------------------
>
>Once you have joined the Accellera VHDL TC, go to the following
>page and login:
>http://www.accellera.org/apps/org/wo.../documents.php
>
>
>To find out the current status of the effort, download the
>document: Requirements Status
>The latest one I looked at resolves to: RequirementsStatus_25Apr2006.xls
>If you look at the statistics in this file, there are 123 approved
>enhancements for this revision and 110 of them have approved
>LRM edits.
>
>Keep in mind, the main reason we miss requirements in language
>design is because either people fail to submit them or people
>who are interested in them fail to participate.
>


To what extent can non-members participate? this is an honest question, I
am not trying to be belligerant. We've all got very limited time and for
those of us who are used to participating in open-source efforts a cursory
glance at the Accellera website reveals a world alien to us so we're more
likely to move along to put our efforts into an open-source project (like
open cores or Icarus Verilog or ghdl...)

Phil
 
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Hans
Guest
Posts: n/a
 
      05-01-2006
Hi Jim,

I know you are actively promoting VHDL-200X (I have seen your MAPLD
presentation . However, you seem to be the only person doing it, I see
hardly any papers, magazine articles, newsgroup postings etc on VHDL-200X
standard. On the 2002 standard, how many VHDL engineers can list the
difference with the 1993 standard? Why do you think that is?

I haven't checked the documents on the Accellera website but from your
presentation it seems that the VHDL-200X standard will be just a clean-up of
the language (PSL being the exception) and something which should have been
added to the 1076-2002 standard? All the goodies that (verification)
engineers need like Constrained Random, OO (so I have been told and a
simpler C interface will be looked at after DAC06? are we looking at another
5 years?

Is Aart de Geus in charge of the committee?

Hans
www.ht-lab.com

"Jim Lewis" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> In their dream world, we would all switch to SystemVerilog.
> No kidding about the marketing effort - this is a no brainer.
> If one can convince the VHDL market to switch to SV, at a
> minimum they will have to upgrade to enhanced licenses and
> this means good revenue. Going further if you can also
> convince VHDL users from your competitor that your tool is
> better and they will switch. Even thinking about this makes
> my eyes see $$$$ and I am not a marketing person
>
> As for delivery from Accellera VHDL TC, DAC of 2006 (July)
> is the required delivery date. Accellera is a different
> model of working than IEEE. We have until 1 month before DAC to
> deliver a standard that is approved by the Accellera VHDL
> TC to the Accellera board. The development process has been
> to prioritize items and work them through the process of
> adding them to the LRM. What is done and approved 1 month
> before DAC gets delivered. So the delivery date is set in
> stone - the number of new features is negotiable, however,
> at this point it looks like we are on track to deliver
> what was started by VHDL-200X-FT plus numerous additional
> enhancements.
>
> BTW, if you are doing fixed and floating point math, the
> Accellera VHDL-2006 adds fixed and floating point
> math packages to the language. This is something that
> you will not find in SystemVerilog.
>
>
> Going further, there is also a working plan to start
> immediately on the next revision. This revision will
> include enhanced verification features such as constrained
> random, OO, coverage, interfaces, and a direct programming
> interface (DPI). It is at this phase where we will have
> the same verification features that SV has. If we can do
> this and maintain the clean language design currently
> enjoyed by VHDL, then I think we will have a clearly
> superior solution.
>
>
> There is another key difference in the Accellera developement
> process that means you will see vendors implementing new
> features sooner. In Accellera, proposals are ranked by the
> user community. As a result, vendors know that these are
> features their user community wants. This is much different
> from having a benevolent expert develop a feature only to
> learn it does not solve the problems users are having
> and as a result, any investment made in implementing the
> feature was wasted since the feature was unused.
>
> Rather than judging Accellera by its current pro SystemVerilog
> front door, hold your judgement for DAC this year. When
> they approve the Accellera VHDL-2006, then you know
> that they are truely a multi-language organization.
>
> I have to say, I had concerns about the pro SystemVerilog
> stance of Accellera. However, I am impressed both with
> the development process and with the effort put forward
> by the VHDL technical committee to get this revision done.
> Personally I have been putting in around 10 hours per week
> on this effort a good portion of this time in meetings,
> and I have been skipping half of the meetings.
>
> Best Regards,
> Jim
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
> Jim Lewis
> Director of Training (E-Mail Removed)
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
>
>
>
>
>
>
>
>>>Has SystemVerilog killed off interest

>>
>>
>> I believe this is happening, look at the amount of effort that EDA
>> companies
>> like Mentor is putting into SystemVerilog (and a bit in SystemC). The
>> momentum of SystemVerilog is now so large that I wonder if companies can
>> be
>> steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
>> Accellera doesn't produce something in say the next 2 years than IMHO
>> VHDL
>> is dead which is a real shame since I prefer it over Verilog.
>>
>> Hans
>> www.ht-lab.com
>>
>> "(E-Mail Removed)" <(E-Mail Removed)> wrote in message
>> news:(E-Mail Removed) oups.com...
>>
>>>Does anyone know the status of VHDL 200x?
>>>When it might be completed?
>>>Has SystemVerilog killed off interest or is it still on track?
>>>

>>


 
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Mike Treseler
Guest
Posts: n/a
 
      05-01-2006
Phil Tomson wrote:

> A quick glance at
> their web page and it's pretty easy to come up with the impression that
> they're working on System Verilog.


My take is that verilog is in much greater
need of an update than is vhdl. If you look
at a list of the new features, there is little
that is not already covered in vhdl93.
It is easier to hype and sell products
with large improvements than sell upgrades.

> What exactly is Accellera and where does their
> revenue come from? (seems to come from membership dues paid by EDA
> companies).


It is an association of companies that
make money on eda software by selling,
promoting, or training.

Now, perhaps Accellera's VHDL 200x efforts are preferrable to
> the way that these sorts of things used to be done (in IEEE
> standardization committees). We'll find out.


The IEEE process was glacial.

> So basically that limits voting influence to the big-boys.


Yes, and like it or not, the big boys in the U.S. use verilog.

-- Mike Treseler
 
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