Velocity Reviews > VHDL > clock doubling?

clock doubling?

bxbxb3
Guest
Posts: n/a

 12-18-2004
can any one tell me how to double the frequency of clock? i have tried the
ckt shown below:
___________________
|____ _____ |
))\--|d q|---|----clk_out
__))/ | |
| | |
global_clk--------|-------|clk__|

clk_out is xored with global clk and given as an input to d flip flop.
will the above circuit work? is so how to write VHDL code for it? i have
tried
1. process(global_clk)
if global_clk'event and global_clk='1' then

2. process(global_clk)
if global_clk'event then

etc etc, but didn't work

Hal Murray
Guest
Posts: n/a

 12-19-2004
>can any one tell me how to double the frequency of clock? i have tried the
>ckt shown below:
> ___________________
> |____ _____ |
> ))\--|d q|---|----clk_out
> __))/ | |
> | | |
> global_clk--------|-------|clk__|

That circuit can't possible work (as a doubler). Your clk goes
into the clock of FF so the output of the FF can't possible run
at more than 1/2 the clk speed.

Peter Alfke of Xilinx described a circuit with the same number of parts.
The output of the XOR gate is the 2x clock, and it goes into the clock
on the FF. The D on the FF goes to the global_clk input.
(It may take another inverter in there someplace.)

That makes a short pulse each time the global_clk changes.

The key idea is that the pulse is long enough to clock the FF
since the output of the FF won't change if the pulse isn't long
enough, and that output is what ends the pulse.

>clk_out is xored with global clk and given as an input to d flip flop.
>will the above circuit work? is so how to write VHDL code for it? i have
>tried

Writing VHDL code is another matter. You may have to add explicit delays.
Be sure your sensitivity lists include both clocks where needed.

>1. process(global_clk)
> if global_clk'event and global_clk='1' then
>
>2. process(global_clk)
> if global_clk'event then
>
>etc etc, but didn't work
>

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