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How does ASIC compiler compile for if..else..

 
 
Weng Tianxiang
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      12-08-2004
Hi,
if(x1 = '1') then -- (1)
R <= y1;
elsif(x2 = '1') then
R <= y1;
....
end if;
The above equations are common in VHDL. For a FPGA chip, VHDL compiler
will generate the following equation (2) for (1):

R <= (x1 and y1) or (not x1 and x2 and y2) + ...; --(2)

And based on FPGA structure, compiler will generate intermediate 4
input LUTs to replace the above equation in its final equation.

I would like to know if equation (1) is compiled into equation (2) for
an ASIC chip by all ASIC VHDL compilers, especially from several
predominate VHDL ASIC compiler companies?

Or any other methods?
The above discussion doesn't include all optimization of (2).

Weng

 
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rickman
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      12-08-2004
Weng Tianxiang wrote:
>
> Hi,
> if(x1 = '1') then -- (1)
> R <= y1;
> elsif(x2 = '1') then
> R <= y1;
> ...
> end if;
> The above equations are common in VHDL. For a FPGA chip, VHDL compiler
> will generate the following equation (2) for (1):
>
> R <= (x1 and y1) or (not x1 and x2 and y2) + ...; --(2)
>
> And based on FPGA structure, compiler will generate intermediate 4
> input LUTs to replace the above equation in its final equation.
>
> I would like to know if equation (1) is compiled into equation (2) for
> an ASIC chip by all ASIC VHDL compilers, especially from several
> predominate VHDL ASIC compiler companies?
>
> Or any other methods?
> The above discussion doesn't include all optimization of (2).


What you call equation 1 is not an equation, it is an HDL description.
It will be translated into equation 2 when compiled. Equation 2 may be
optimized into anything equivalent for implementation as the compiler
sees fit.

--

Rick "rickman" Collins

http://www.velocityreviews.com/forums/(E-Mail Removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
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Tom Verbeure
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      12-09-2004
Yes, an ASIC synthesizer will do the same thing as an FPGA synthesizer:
it will create logic that matches your hdl description. If he has
additional information that can legally allow him to optimize, it may
do so, but given only the information that you have given, it should do
exactly what you requested. (But of course, you already knew that.
)

Tom

 
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