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Beginners questions for addition

Clemens Bosch
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I have the following problem: I want to perform an addition in one clk
cycle, therefore I have implemented a modul add which performs me this
bitwise. I have got an input vector whereas bit I contains the bits for
operand a, whereas I+1 contains the bits for operand b. Therfore first of
all I want to extract the values and save it in a signal a, respectivly b
which is then the input for my adder. Before I add it I want to shift signal
a by 4 positions. Here is the way I thought it would work:

signal a,b,term1: std_ulogic_vector((width-1) downto 0) := (others => '0');


variable av, bv: std_logic_vector((2*width-1) downto 0);

for I in 0 to (width-1) loop
av(I) := inp(I);
bv(I) := inp(2*I);
end loop;
a <= av;
b <= bv;
end process;

term1 <= a(width-5 downto 0) & "0000";

add1: for I in 0 to (width-1) generate
add1_I:add port map(a(I),b(I),result(I));
end generate

So I have to do it this way, that the values are extracted first and stored
in a variable for later tasks. I cant feed them directly to the adder. So
can perhaps someone explain a good way to solve this problem? I just want to
extract the values as soon as the input changes, and then this values have
to be shifted before the are put into a adder chain and this should somehow
be performed in one clk cycle.

Thanks for every hint

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