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Verilog Code

 
 
dcell
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      11-21-2004
Could anyone look at my code here and tell me what the HELL is wrong
with it?

I keep getting an error complaining about endmodule. I'm about ready
to destroy something.

Thanks.

module barrel(data_in, shift, data_out) ;
input [3:0]data_in;
input [1:0]shift;
output [3:0]data_out;
reg [3:0]data_out;

always@(data_in or shift)

case(shift)
0: data_out <= data_in ;
1: data_out <= data_in*2 ;
2: data_out <= data_in*4 ;
3: data_out <= data_in*8 ;

endmodule
 
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Uwe Bonnes
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      11-21-2004
dcell <(E-Mail Removed)> wrote:
: Could anyone look at my code here and tell me what the HELL is wrong
: with it?

: I keep getting an error complaining about endmodule. I'm about ready
: to destroy something.

: Thanks.

: module barrel(data_in, shift, data_out) ;
: input [3:0]data_in;
: input [1:0]shift;
: output [3:0]data_out;
: reg [3:0]data_out;

: always@(data_in or shift)

: case(shift)
: 0: data_out <= data_in ;
: 1: data_out <= data_in*2 ;
: 2: data_out <= data_in*4 ;
: 3: data_out <= data_in*8 ;

: endmodule

You're missing the 'endcase' statement

Bye
--
Uwe Bonnes http://www.velocityreviews.com/forums/(E-Mail Removed)-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
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