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Hello,



I am trying to interface a Dual Port RAM (SRAM) with a CPLD. The
memory part number is

IDT 70T633/1S. Now, I am generating the Read /Write cycles for the
memory but i am unable to

see the correct data!

My question is that I am not seeing the data because Am I not
holding the data long enough inside

the CPLD or some other VHDL reason...... Please Advice!

I reduced the code to just write one memory location and reading the
same memory location..


-- Reading Program

Process ( State_A )

Begin
Case State_A is

When A0=>

LBL <='1';
UBL <='1';
CE0 <='1';
CE1 <='0';
Read_write <='1';
Output_Enable <='1';
Data_bus <="ZZZZZZZZZZZZZZ";
Address_bus <="0000000000000000111";

nextstate_A <= A1;


When A1=>
LBL <='0';
UBL <='0';
CE0 <='0';
CE1 <='1';
Read_write <='1';
Output_Enable <='0';
Address_bus <="0000000000000000111";

nextstate_A <= A0



When others =>

nextstate_A <= A0;

End Case;

End Process;

------------------------------------------------------------------------------------------------------------
-- Writing Program

Process (State2)
Begin

Case State2 is

When G0=>

UBL <='1';
LBL <='1';
CE0 <='1';
CE1 <='0';
Output_Enable <='1';
Read_write <='1';
Data_Bus <= "01010101010101";
Address_bus <="0000000000000000111";



nextstate2 <=G1;

When G1=>

Data_Bus <= "01010101010101";
Address_bus <="0000000000000000111";
UBL <='1';
LBL <='1';
CE0 <='1';
CE1 <='0';
Output_Enable <='1';
Read_write <='1';

nextstate2 <=G2;

When G2=>

Address_bus <="0000000000000000111";
Data_Bus <= "01010101010101";
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable <='1';
Read_write <='0';

nextstate2 <=G1;

When others =>

nextstate2 <=G0;

End case;
End Process;


Regards
john

Hi John,
Its difficult to say just by looking at the code whether the
write/read will be successful to the memory block. If I may suggest,
have you tried simulating with its verilog or vhdl models.

Hi,

you make the assignment
nextstate_A <= A1;

Do you have a clocked process you did not show to us?

Rgds
André


(john) wrote in message news:<. com>...
> Hello,
>
>
>
> I am trying to interface a Dual Port RAM (SRAM) with a CPLD. The
> memory part number is
>
> IDT 70T633/1S. Now, I am generating the Read /Write cycles for the
> memory but i am unable to
>
> see the correct data!
>
> My question is that I am not seeing the data because Am I not
> holding the data long enough inside
>
> the CPLD or some other VHDL reason...... Please Advice!
>
> I reduced the code to just write one memory location and reading the
> same memory location..
>
>
> -- Reading Program
>
> Process ( State_A )
>
> Begin
> Case State_A is
>
> When A0=>
>
> LBL <='1';
> UBL <='1';
> CE0 <='1';
> CE1 <='0';
> Read_write <='1';
> Output_Enable <='1';
> Data_bus <="ZZZZZZZZZZZZZZ";
> Address_bus <="0000000000000000111";
>
> nextstate_A <= A1;
>
>
> When A1=>
> LBL <='0';
> UBL <='0';
> CE0 <='0';
> CE1 <='1';
> Read_write <='1';
> Output_Enable <='0';
> Address_bus <="0000000000000000111";
>
> nextstate_A <= A0
>
>
>
> When others =>
>
> nextstate_A <= A0;
>
> End Case;
>
> End Process;
>
> ------------------------------------------------------------------------------------------------------------
> -- Writing Program
>
> Process (State2)
> Begin
>
> Case State2 is
>
> When G0=>
>
> UBL <='1';
> LBL <='1';
> CE0 <='1';
> CE1 <='0';
> Output_Enable <='1';
> Read_write <='1';
> Data_Bus <= "01010101010101";
> Address_bus <="0000000000000000111";
>
>
>
> nextstate2 <=G1;
>
> When G1=>
>
> Data_Bus <= "01010101010101";
> Address_bus <="0000000000000000111";
> UBL <='1';
> LBL <='1';
> CE0 <='1';
> CE1 <='0';
> Output_Enable <='1';
> Read_write <='1';
>
> nextstate2 <=G2;
>
> When G2=>
>
> Address_bus <="0000000000000000111";
> Data_Bus <= "01010101010101";
> UBL <='0';
> LBL <='0';
> CE0 <='0';
> CE1 <='1';
> Output_Enable <='1';
> Read_write <='0';
>
> nextstate2 <=G1;
>
> When others =>
>
> nextstate2 <=G0;
>
> End case;
> End Process;
>
>
> Regards
> john

Hi,
Yes, I have a clocked process!


Thanks
john

(ALuPin) wrote in message news:<. com>...
> Hi,
>
> you make the assignment
> nextstate_A <= A1;
>
> Do you have a clocked process you did not show to us?
>
> Rgds
> André
>
>
> (john) wrote in message news:<. com>...
> > Hello,
> >
> >
> >
> > I am trying to interface a Dual Port RAM (SRAM) with a CPLD. The
> > memory part number is
> >
> > IDT 70T633/1S. Now, I am generating the Read /Write cycles for the
> > memory but i am unable to
> >
> > see the correct data!
> >
> > My question is that I am not seeing the data because Am I not
> > holding the data long enough inside
> >
> > the CPLD or some other VHDL reason...... Please Advice!
> >
> > I reduced the code to just write one memory location and reading the
> > same memory location..
> >
> >
> > -- Reading Program
> >
> > Process ( State_A )
> >
> > Begin
> > Case State_A is
> >
> > When A0=>
> >
> > LBL <='1';
> > UBL <='1';
> > CE0 <='1';
> > CE1 <='0';
> > Read_write <='1';
> > Output_Enable <='1';
> > Data_bus <="ZZZZZZZZZZZZZZ";
> > Address_bus <="0000000000000000111";
> >
> > nextstate_A <= A1;
> >
> >
> > When A1=>
> > LBL <='0';
> > UBL <='0';
> > CE0 <='0';
> > CE1 <='1';
> > Read_write <='1';
> > Output_Enable <='0';
> > Address_bus <="0000000000000000111";
> >
> > nextstate_A <= A0
> >
> >
> >
> > When others =>
> >
> > nextstate_A <= A0;
> >
> > End Case;
> >
> > End Process;
> >
> > ------------------------------------------------------------------------------------------------------------
> > -- Writing Program
> >
> > Process (State2)
> > Begin
> >
> > Case State2 is
> >
> > When G0=>
> >
> > UBL <='1';
> > LBL <='1';
> > CE0 <='1';
> > CE1 <='0';
> > Output_Enable <='1';
> > Read_write <='1';
> > Data_Bus <= "01010101010101";
> > Address_bus <="0000000000000000111";
> >
> >
> >
> > nextstate2 <=G1;
> >
> > When G1=>
> >
> > Data_Bus <= "01010101010101";
> > Address_bus <="0000000000000000111";
> > UBL <='1';
> > LBL <='1';
> > CE0 <='1';
> > CE1 <='0';
> > Output_Enable <='1';
> > Read_write <='1';
> >
> > nextstate2 <=G2;
> >
> > When G2=>
> >
> > Address_bus <="0000000000000000111";
> > Data_Bus <= "01010101010101";
> > UBL <='0';
> > LBL <='0';
> > CE0 <='0';
> > CE1 <='1';
> > Output_Enable <='1';
> > Read_write <='0';
> >
> > nextstate2 <=G1;
> >
> > When others =>
> >
> > nextstate2 <=G0;
> >
> > End case;
> > End Process;
> >
> >
> > Regards
> > john