Velocity Reviews > VHDL > Newbie: Synchronize a time value to another clock

# Newbie: Synchronize a time value to another clock

Manfred Balik
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Posts: n/a

 11-12-2004
I'm using an even-numbered clock to generate a time value.
How can I synchronize this time value to a part in the code using an other
odd-numbered clock ?
Thanks, Manfred

Paul Uiterlinden
Guest
Posts: n/a

 11-12-2004
Manfred Balik wrote:
> I'm using an even-numbered clock to generate a time value.
> How can I synchronize this time value to a part in the code using an other
> odd-numbered clock ?

What are even/odd-numbered clocks?
What is a time value?

Paul.

Manfred Balik
Guest
Posts: n/a

 11-12-2004
even-numbered clock: 40 MHz
odd-numbered clock: 27.678...MHz
time value: like in Unix "timespec" - 16bit for ns, 16bit for s
I can't make this time value from the 27.678...MHz-clock, because the
duration of one clock is not equal to nanoseconds.
So I want to make the time value by an 40MHz-clock, but I need the value in
the 27.678...MHz-clock-domain.
Thanks, Manfred

"Paul Uiterlinden" <(E-Mail Removed)> schrieb im Newsbeitrag
news:cn2ac9\$73h\$(E-Mail Removed)...
> Manfred Balik wrote:
>> I'm using an even-numbered clock to generate a time value.
>> How can I synchronize this time value to a part in the code using an
>> other odd-numbered clock ?

>
> What are even/odd-numbered clocks?
> What is a time value?
>
> Paul.

Hal Murray
Guest
Posts: n/a

 11-12-2004
>So I want to make the time value by an 40MHz-clock, but I need the value in
>the 27.678...MHz-clock-domain.

Plan 1:
Take the 40 MHz clock and divide it down so that it is slow enough
to process in the 27 MHz domain. Say 10 MHz for example. Send
that across (watch metastability and such) and update the clock
every time you see an edge.

Plan 2:
How much accuracy do you need? (The crystal isn't perfect.)
Just use a big counter - lots of bits in the fraction part.
Every time the 27 MHz clock ticks you add a magic constant.
The fraction part will overflow occasionally and correct
for not having simple integer values.

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Nils Strandberg
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Posts: n/a

 11-12-2004
Manfred Balik wrote:
> even-numbered clock: 40 MHz
> odd-numbered clock: 27.678...MHz
> time value: like in Unix "timespec" - 16bit for ns, 16bit for s
> I can't make this time value from the 27.678...MHz-clock, because the
> duration of one clock is not equal to nanoseconds.
> So I want to make the time value by an 40MHz-clock, but I need the value in
> the 27.678...MHz-clock-domain.
> Thanks, Manfred
>
>
> "Paul Uiterlinden" <(E-Mail Removed)> schrieb im Newsbeitrag
> news:cn2ac9\$73h\$(E-Mail Removed)...
>
>>Manfred Balik wrote:
>>
>>>I'm using an even-numbered clock to generate a time value.
>>>How can I synchronize this time value to a part in the code using an
>>>other odd-numbered clock ?

>>
>>What are even/odd-numbered clocks?
>>What is a time value?
>>
>>Paul.

Well, depends a lot on how you are going to implement it, if it is a
FPGA that
supports a FIFO with separate read and write clocks it should be very
easy. Just
divide your write clock down to 10 or 20 MHz and you will not have any
problem.

If your design is based on something else, we have to have another think.

/NS

Paul Uiterlinden
Guest
Posts: n/a

 11-15-2004
Manfred Balik wrote:
> even-numbered clock: 40 MHz
> odd-numbered clock: 27.678...MHz
> time value: like in Unix "timespec" - 16bit for ns, 16bit for s
> I can't make this time value from the 27.678...MHz-clock, because the
> duration of one clock is not equal to nanoseconds.
> So I want to make the time value by an 40MHz-clock, but I need the value in
> the 27.678...MHz-clock-domain.

OK, so your main problem is to get this 16 bit value accros the clock
boundary, from the area running on the fast clock to the area on the
slow clock.

Because this value is generated with a different clock, you cannot clock
it in without further measures. The best way is to create a single
data-valid signal and solve the meta-stability problem on that signal.
That means that the signal must be at least two 40 MHz clock periods
long (otherwise it can be missed, clocking it in at 27 MHz) and this
signal must be clocked in with two cascaded flip-flops (for the
meta-stability problem). Also make sure that the source of the
data-valid signal is a flip-flop, so the transistion across the clock
boundary is directly from flip-flop to flip-flop, without any logic in
between (again: to avoid meta-stability problems).

Perhaps you'll also need a kind of request signal (indicating "give me a
new value") going from the 27 MHz area to the 40 MHz area. If so, the
meta-stablity problem should be considered there as well.

Paul.