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Re: I can't set inout port in vhdl code

 
 
rickman
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      11-12-2004
suntthekid wrote:
>
> Hello,
> I have a problem about set up inout port when i simulate vhdl code It
> is not work
> so i want to know how to write vhdl code ( set pin to inout and
> it is work) also i try to use tristate but It is not work too. maybe i
> miss something in the code and i don't know. help me please


You might also try posting this to comp.lang.vhdl. What the heck, I'll
do it for you...

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Mike Treseler
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      11-12-2004
suntthekid wrote:

>> I have a problem about set up inout port when i simulate vhdl code It
>>is not work


Here's an example:

http://groups.google.com/groups?q=vhdl+oe_demo+op_t

-- Mike Treseler
 
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