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VHDL - Synthesis of VHDL RTL including recursive functions |
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11-09-2004, 12:45 PM
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#1 |
Synthesis of VHDL RTL including recursive functions
Hi
When a VHDL module with recursive functions is synthetised, what is exactly happening? The result is available during the same clock cycle, so I would expect the synthesis tool to translate the recursive nature of the algorithm into a 'spacial' algorithm (e.g. if the recusion has a depth of 10, then there will be 10 'stages' on the silicon). Am I totally wrong here? Where can I find further details on that? Thanks, gil gpi5 |
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11-09-2004, 02:44 PM
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#2 |
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Posts: n/a
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Re: Synthesis of VHDL RTL including recursive functions
gpi5 wrote:
> When a VHDL module with recursive functions is synthetised, what is > exactly happening? Loops of all types are an editing convenience. All loops are unrolled long before anything physical happens. > Where can I find further details on that? http://groups.google.com/groups?q=vh...n+OR+recursive -- Mike Treseler Mike Treseler |
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