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Synthesis of VHDL RTL including recursive functions

 
 
gpi5
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      11-09-2004
Hi

When a VHDL module with recursive functions is synthetised, what is
exactly happening?
The result is available during the same clock cycle, so I would expect the
synthesis tool to translate the recursive nature of the algorithm into a
'spacial' algorithm (e.g. if the recusion has a depth of 10, then there
will be 10 'stages' on the silicon). Am I totally wrong here?

Where can I find further details on that?
Thanks,
gil


 
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Mike Treseler
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      11-09-2004
gpi5 wrote:

> When a VHDL module with recursive functions is synthetised, what is
> exactly happening?


Loops of all types are an editing convenience.
All loops are unrolled long before anything physical happens.

> Where can I find further details on that?


http://groups.google.com/groups?q=vh...n+OR+recursive


-- Mike Treseler
 
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