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john
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Posts: n/a
 
      11-05-2004
Hello,

I am trying to interface a USB receiver chip with the FPGA. The USB
chip can only allow unidirection
communications. it just outputs eight bit of data at 12 MHz at each
rising edge of the USB clock in brust
mode. The scheme I used is simple but my State machine is getting lost
and screwing up the count of the counter. some times It works
sometimes it does not work!
I am using the counter to generate addressess for the Dual port RAM.
My VHDL comlplier also ignoring the intialization
of the signal Flag1 and I do not know why? Please Advice!

Thanks very much.
Regards
john






signal State : unsigned(7 downto 0);
signal nextstate : unsigned(7 downto 0);
constant E0 : unsigned(7 downto 0):="00000000";
constant E1 : unsigned(7 downto 0):="00000001";
constant E2 : unsigned(7 downto 0):="00000010";
constant E3 : unsigned(7 downto 0):="00000011";


Signal State1 : unsigned(7 downto 0);
Signal nextstate1 : unsigned (7 downto 0);
constant F0: unsigned(7 downto 0):="00000000";
constant F1: unsigned(7 downto 0):="00000001";


Signal inc: std_logic:='0';
Signal eq_signal : std_logic:='1';
Signal Reset_A : std_logic;
Signal counter_clock : std_logic;

Signal USB_port : unsigned ( 7 downto 0);
Signal Flag1 : std_logic:='0';

Begin

Data_Bus<="00000000000000";
C0: counter port map (Address_bus,
Data_in,DPR_CLK,inc,eq_signal,Reset_A);


Process(State1,nextstate1)
Begin

Case State1 is


When F0 =>
Flag1 <='0';
nextstate1 <= F1;

When F1 =>
Flag1 <='1';
nextstate1<=F0;

When others =>

Null;

End Case;
End Process;
-------------------------------------------
Process(USB_CLK,State1,nextstate1)
Begin

If (USB_CLK'event And USB_CLK='1') Then

State1 <= nextstate1;

End If;
End Process;
------------------------------------------
Process (State,nextstate,SM_DIR,Flag1)
Begin

Case State is

When E0=>
Reset_A<='1';
inc<='0';
UBL <='1';
LBL <='1';
CE0 <='1';
CE1 <='0';
Output_Enable<='1';
Read_write <='1';
nextstate<=E1;


When E1=>
If (Flag1='1')Then
Reset_A<='0';
UBL <='1';
LBL <='1';
CE0 <='1';
CE1 <='0';
Output_Enable<='1';
Read_write <='1';
inc<='1';
nextstate<=E2;
Else
nextstate<=E1;
End If;

When E2=>
Reset_A<='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='1';
Read_write <='0';
inc<='0';
nextstate<=E3;

When E3=>
If (Flag1='0')Then
Reset_A<='0';
UBL <='0';
LBL <='0';
CE0 <='0';
CE1 <='1';
Output_Enable<='1';
Read_write <='0';
inc<='0';
nextstate<=E1;
Else
nextstate<=E3;
End If;

When others =>

NULL;
End case;
End Process;

Process (DPR_CLK,State,nextstate)
Begin

If (DPR_CLK'event And DPR_CLK='1') Then

State <= nextstate;
End If;
End Process;
End DPR_ARCH;
 
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rickman
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Posts: n/a
 
      11-05-2004
john wrote:
>
> Hello,
>
> I am trying to interface a USB receiver chip with the FPGA. The USB
> chip can only allow unidirection
> communications. it just outputs eight bit of data at 12 MHz at each
> rising edge of the USB clock in brust
> mode. The scheme I used is simple but my State machine is getting lost
> and screwing up the count of the counter. some times It works
> sometimes it does not work!
> I am using the counter to generate addressess for the Dual port RAM.
> My VHDL comlplier also ignoring the intialization
> of the signal Flag1 and I do not know why? Please Advice!


....snip...

> Signal USB_port : unsigned ( 7 downto 0);
> Signal Flag1 : std_logic:='0';
>
> Begin
>
> Data_Bus<="00000000000000";
> C0: counter port map (Address_bus,
> Data_in,DPR_CLK,inc,eq_signal,Reset_A);
>
> Process(State1,nextstate1)
> Begin
>
> Case State1 is
>
> When F0 =>
> Flag1 <='0';
> nextstate1 <= F1;
>
> When F1 =>
> Flag1 <='1';
> nextstate1<=F0;
>
> When others =>
>
> Null;
>
> End Case;
> End Process;


I am not sure how you can tell that Flag1 initialization is being
ignored. Flag1 is assigned a value in a combinatorial process. At
least I assume that is what you intended. In reality you have inferred
a level sensitive latch. You should also be getting warnings about your
sensitivity list in this process. Nextstate1 should not be in it while
F1 and F0 *should* be in it.

If Flag1 is intended to be combinatorial, then you need to define a
value for Flag1 for the "others" condition. Regardless, if it is
combinatorial, it will *always* be assigned a value based on the inputs
to its assignments and the initial value will be ignored. Initial
values are only useful on signals assigned values in clocked processes.


--

Rick "rickman" Collins

http://www.velocityreviews.com/forums/(E-Mail Removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
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john
Guest
Posts: n/a
 
      11-07-2004
Hello,
Thank u ver much for ur reply! I meant to ask you that the complier is
giving me the message that it is ignoring the intialization of the
signal Flag1. I do not know why is it doing it?
Secondly, my question is that the sequential machine in the second
process having "state" equal to E0,E1.E2 is loosing its direction. And
I am trying to find out the answer that is it because of the Flag1
because thats the only signal common bewtween rwo processes.
My third question is that is it the right way to implement it... If I
remove the USB process then Read Write control signals for the memory
works ok but asa I insert the USB process I loose the direction of the
machine...
Thanks
john
rickman <(E-Mail Removed)> wrote in message news:<(E-Mail Removed)>...
> john wrote:
> >
> > Hello,
> >
> > I am trying to interface a USB receiver chip with the FPGA. The USB
> > chip can only allow unidirection
> > communications. it just outputs eight bit of data at 12 MHz at each
> > rising edge of the USB clock in brust
> > mode. The scheme I used is simple but my State machine is getting lost
> > and screwing up the count of the counter. some times It works
> > sometimes it does not work!
> > I am using the counter to generate addressess for the Dual port RAM.
> > My VHDL comlplier also ignoring the intialization
> > of the signal Flag1 and I do not know why? Please Advice!

>
> ...snip...
>
> > Signal USB_port : unsigned ( 7 downto 0);
> > Signal Flag1 : std_logic:='0';
> >
> > Begin
> >
> > Data_Bus<="00000000000000";
> > C0: counter port map (Address_bus,
> > Data_in,DPR_CLK,inc,eq_signal,Reset_A);
> >
> > Process(State1,nextstate1)
> > Begin
> >
> > Case State1 is
> >
> > When F0 =>
> > Flag1 <='0';
> > nextstate1 <= F1;
> >
> > When F1 =>
> > Flag1 <='1';
> > nextstate1<=F0;
> >
> > When others =>
> >
> > Null;
> >
> > End Case;
> > End Process;

>
> I am not sure how you can tell that Flag1 initialization is being
> ignored. Flag1 is assigned a value in a combinatorial process. At
> least I assume that is what you intended. In reality you have inferred
> a level sensitive latch. You should also be getting warnings about your
> sensitivity list in this process. Nextstate1 should not be in it while
> F1 and F0 *should* be in it.
>
> If Flag1 is intended to be combinatorial, then you need to define a
> value for Flag1 for the "others" condition. Regardless, if it is
> combinatorial, it will *always* be assigned a value based on the inputs
> to its assignments and the initial value will be ignored. Initial
> values are only useful on signals assigned values in clocked processes.
>
>
> --
>
> Rick "rickman" Collins
>
> (E-Mail Removed)
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX

 
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