how to get SDF file from netlist

Hi all,
after syntheising with design Compiler , I manually changed a cell
from the netlist(changed the gate strength)... How can get an SDF file
for this new netlist...using DC
thanks
whizkid

whizkid

(whizkid) writes:

> Hi all,
> after syntheising with design Compiler , I manually changed a cell
> from the netlist(changed the gate strength)... How can get an SDF file
> for this new netlist...using DC

You get and SDF file from your place and route tool.

Petter
--
__________________________________________________ ______________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com

Petter Gustad

whizkid wrote:
> Hi all,
> after syntheising with design Compiler , I manually changed a cell
> from the netlist(changed the gate strength)... How can get an SDF file
> for this new netlist...using DC
> thanks
> whizkid

Start DC, setup your libraries, read in the verilog netlist file,
setup your wireload models (or even the original constraints you used),
then you should be able to write out a SDF file. But then, as Petter
mentioned, it is better to get SDF output from layout extraction.
Output from DC is not very accurate (since wire delay is modeled
by wire load model).

Joe

Joe