Go Back   Velocity Reviews > Newsgroups > VHDL
pipelining pipelining
User Name
Password
Register FAQ Members List Calendar Search Today's Posts Mark Forums Read

Reply

VHDL - pipelining
 
Thread Tools Search this Thread
Old 11-05-2004, 05:35 AM   #1
Default pipelining


hi,

Can anyone please give the VHDL code for the following pipelined
architecture:

Input-->portmap"mmm"-->register1-->portmap"mmm"->register2

--> portmap"mmm" -> output





tulip
  Reply With Quote
Reply

« Sequential Machines | how to get SDF file from netlist »

Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts
vB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off


Contact Us - - Archive - Privacy Statement - Top


SEO by vBSEO 3.3.2 ©2009, Crawlability, Inc.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46