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VHDL - Physical Compiler Vs Design Complier

 
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Old 11-03-2004, 12:02 PM   #1
Default Physical Compiler Vs Design Complier


Can anyone pointout the practical differences? I am now synthesising a
design with TSMC 13u library with Design Compiler? What difference in
results can I expect if I use physical Compiler.

thanks
whizkid


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Old 11-03-2004, 05:55 PM   #2
Tom Verbeure
 
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Default Re: Physical Compiler Vs Design Complier

If you provide a floorplan to Physical compiler, it will estimate the
loading of nets according to actual placement of cells instead of
statistical wireload models. This generally results in faster maximum
speeds of the final design.

Tom



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