How to preserve net names in DC while synthesis

Hi all,
Does anyone know how to preserve the "wire" names in the netlist so
that it is wasy for debugging the netlist. I used dont_touch command
with net name , but I think this will reduce the logic optimization
by the tool.. what do u think

thanks
whizkid

whizkid

> Does anyone know how to preserve the "wire" names in the netlist so
> that it is wasy for debugging the netlist. I used dont_touch command
> with net name , but I think this will reduce the logic optimization
> by the tool.. what do u think

There's no easy way if you want the best optimization. The signals
connected to registers are usually preserved, but after that you're
more or less at the mercy of the synthesis tool. If you absolutely need
to get some signals preserved, I'm not sure dont_touch will help that
much. Probably the best way is to bring internal signals to the top as
output ports and ask DC not to optimize them away if they're not
connected. I assume there must a flag for this somewhere, though I
haven't really looked into it.

We've pretty much given up on even trying to get a nice match and have
formal equivalence check validate the correctness of the netlist. Yes,
this makes netlist hacking extremely painful: just try to make sure
your RTL is correct.

Tom

Tom Verbeure