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VHDL - concatenation problem + difference between mod and rem

 
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Old 10-31-2004, 02:28 PM   #1
Default concatenation problem + difference between mod and rem


Hi all,

1) Why it is not possible to concatenate two bits to make a vector in
the following example.

signal s1,s2 :bit;

case (s1 & s2 ) is
WHEN "00" => ...


end case;

2) What is the advantage in having two operators(mod and rem ) which
seems almost similar.Is there any good reason(application) where they
have specific meaning.

Thanks in advance.

Regards,
Mohammed A.khader.


Mohammed khader
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Old 11-01-2004, 09:26 AM   #2
Alan Fitch
 
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Default Re: concatenation problem + difference between mod and rem

"Mohammed khader" <> wrote in message
news: om...
> Hi all,
>
> 1) Why it is not possible to concatenate two bits to make a vector

in
> the following example.
>
> signal s1,s2 :bit;
>
> case (s1 & s2 ) is
> WHEN "00" => ...
>
>
> end case;
>


Because the data type is not determinable by the compiler.

> 2) What is the advantage in having two operators(mod and rem ) which
> seems almost similar.Is there any good reason(application) where

they
> have specific meaning.
>


They differ in behaviour for signed values.

Alan


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