![]() |
|
|
|||||||
![]() |
VHDL - concatenation problem + difference between mod and rem |
|
|
Thread Tools | Search this Thread |
|
|
#1 |
|
Hi all,
1) Why it is not possible to concatenate two bits to make a vector in the following example. signal s1,s2 :bit; case (s1 & s2 ) is WHEN "00" => ... end case; 2) What is the advantage in having two operators(mod and rem ) which seems almost similar.Is there any good reason(application) where they have specific meaning. Thanks in advance. Regards, Mohammed A.khader. Mohammed khader |
|
|
|
|
#2 |
|
Posts: n/a
|
"Mohammed khader" <> wrote in message news: om... > Hi all, > > 1) Why it is not possible to concatenate two bits to make a vector in > the following example. > > signal s1,s2 :bit; > > case (s1 & s2 ) is > WHEN "00" => ... > > > end case; > Because the data type is not determinable by the compiler. > 2) What is the advantage in having two operators(mod and rem ) which > seems almost similar.Is there any good reason(application) where they > have specific meaning. > They differ in behaviour for signed values. Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. Alan Fitch |
|