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VHDL - doubt regarding port mapping

 
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Old 10-29-2004, 08:03 AM   #1
Default doubt regarding port mapping


My code is

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mod_exp is
Port ( T : in std_logic_vector(7 downto 0);
E : in std_logic_vector(7 downto 0);
M0 : in std_logic_vector(7 downto 0);
P,G1,G2 : buffer std_logic_vector(7 downto 0);
Gout : buffer std_logic_vector(7 downto 0)
);
end mod_exp;

architecture structural of mod_exp is

component str
port(A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
M : in std_logic_vector(7 downto 0);
R : buffer std_logic_vector(7 downto 0)
);
end component;
signal C,one:std_logic_vector(7 downto 0);
begin
C<='00000100'; one<='00000001';
r0:str port map(C,T,M0,P); --line 1
r1:str port map(C,one,M0,G1); --line 2
r2:str port map(G1,G1,M0,Gout); --line 3

end structural;

IN THE ABOVE CODE, I GOT THE OUTPUTS P AND G1 IN LINE 1 AND LINE 2. BUT I
AM NOT GETTING THE OUTPUT Gout IN LINE 3. I AM GETTING 0XXXXXXX AS OUTPUT
FOR Gout. CAN ANYONE SUGGEST THE SOLUTION.





tulip
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Old 10-29-2004, 06:37 PM   #2
rickman
 
Posts: n/a
Default Re: doubt regarding port mapping
tulip wrote:
>
> My code is
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity mod_exp is
> Port ( T : in std_logic_vector(7 downto 0);
> E : in std_logic_vector(7 downto 0);
> M0 : in std_logic_vector(7 downto 0);
> P,G1,G2 : buffer std_logic_vector(7 downto 0);
> Gout : buffer std_logic_vector(7 downto 0)
> );
> end mod_exp;
>
> architecture structural of mod_exp is
>
> component str
> port(A : in std_logic_vector(7 downto 0);
> B : in std_logic_vector(7 downto 0);
> M : in std_logic_vector(7 downto 0);
> R : buffer std_logic_vector(7 downto 0)
> );
> end component;
> signal C,one:std_logic_vector(7 downto 0);
> begin
> C<='00000100'; one<='00000001';
> r0:str port map(C,T,M0,P); --line 1
> r1:str port map(C,one,M0,G1); --line 2
> r2:str port map(G1,G1,M0,Gout); --line 3
>
> end structural;
>
> IN THE ABOVE CODE, I GOT THE OUTPUTS P AND G1 IN LINE 1 AND LINE 2. BUT I
> AM NOT GETTING THE OUTPUT Gout IN LINE 3. I AM GETTING 0XXXXXXX AS OUTPUT
> FOR Gout. CAN ANYONE SUGGEST THE SOLUTION.


You don't say what the values of G1 or T are. You also did not provide
the code for the str module. What does str do?

While we are at it, I don't see where E is used and I don't see where G2
is assigned a value.

--

Rick "rickman" Collins


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removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
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rickman
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