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Cumbersome Signal Assignment

 
 
Eric
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      10-28-2004
Hi,

I have been unable to work out how to use a user-defined type in an
entities port description. Is this possible?

I'd like to access the port signals as an array of std_logic_vector
instead of one large std_logic_vector. The way I do this at present is
a little cumbersome and I just wanted to check there isn't a better
way of achieving it. Here is what I do right now:

I use a std_logic_vector for the port description and a signal array
of std_logic_vectors inside the architecture. A for loop then ties the
two sets of signals together. So, say we implement twelve 3 bit
counters inside the entity it might look something like this:

entity counters is
port(Clock : in std_logic;
counter3port : out std_logic_vector (35 downto 0)
-- etc.
);
end counters;

architecture structure of counters is
type counter3array is array (0 to 11) of std_logic_vector (2 downto
0);
signal counter3 : counter3array;
begin
-- Translate between the userdefined type and the port type
process (counter3) begin
for i in 12 downto 1 loop
counter3port((i*3)-1 downto (i*3)-3)<=counter3(i-1);
end loop;
end process;

-- Implement the 12 three bit counters etc. here

end structure;

Is there a simpler way of accessing the port signals as an array?

Eric.
 
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mike_treseler
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      10-28-2004
If you really need all the counts in the top entity
then the way you've done it can't be simplified much.
If the counts are used internally but not directly output
to pins, I would make them process variables.

-- Mike Treseler


 
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Eric
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      10-29-2004
"mike_treseler" <tres@fl_ke.com> wrote:
> If you really need all the counts in the top entity
> then the way you've done it can't be simplified much.
> If the counts are used internally but not directly output
> to pins, I would make them process variables.


Thanks for your reply. As I suspected it turns out you can simplify
it.

In my package definition I include the type declaration:

type COUNT3_ARRAY is array (11 downto 0) of STD_LOGIC_VECTOR(2 downto
0);

The entity declaration now looks something like this:

entity counters is
port(Clock : in std_logic;
counter3port : count3_array;
-- etc.
);
end counters;

I no longer have to manually translate between std_logic_vector and an
array of std_logic_vectors each time I go through an entity interface.

Eric.
 
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